Memory devices with a connecting region having a band gap lower than a band gap of a body region
Memory devices are shown that include a body region and a connecting region that is formed from a semiconductor with a lower band gap than the body region. Connecting region configurations can provide increased gate induced drain leakage during an erase operation. Configurations shown can provide a reliable bias to a body region for memory operations such as erasing, and containment of charge in the body region during a boost operation.
1. A memory device, comprising:
a body region comprising a semiconductor having a first band gap;
a source region coupled to a first end of the body region, and a drain region coupled to a second end of the body region;
a plurality of gates along a length of the body region, each of the plurality of gates being separated from the body region by at least a respective charge storage structure;
a connecting region comprising a semiconductor having a second band gap, the second band gap being lower than the first band gap, the connecting region coupling the source region to the body region; and
a source select gate adjacent to the body region and the connecting region.
2. The memory device of claim 1 , wherein the body region is oriented vertically.
3. The memory device of claim 1 , wherein the body region is oriented horizontally.
4. The memory device of claim 1 , wherein the body region forms a “U” shape with upward facing ends.
5. The memory device of claim 1 , wherein the body region comprises doped silicon.
6. The memory device of claim 5 , wherein the body region comprises p type silicon.
7. The memory device of claim 1 , wherein the connecting region comprises a semiconductor chosen from group consisting of germanium, gallium antimonide, indium nitride, indium arsenide, lead sulfide, lead selenide, lead telluirde, and silicon germanium.
8. The memory device of claim 1 , wherein the connecting region is directly coupled to the source region and wherein the connecting region is directly coupled to the body region.
9. The memory device of claim 1 , wherein the body region comprises silicon and the connecting region comprises silicon germanium.
10. The memory device of claim 9 , wherein the silicon germanium region comprises epitaxial silicon germanium.
11. The memory device of claim 10 , wherein the epitaxial silicon germanium is Si x Ge 1-x where x is approximately 0.5.
12. The memory device of claim 1 , wherein the connecting region comprises a source connecting region, and further comprising:
a drain connecting region comprising a semiconductor having a band gap lower than the first band gap, the drain connecting region coupling the drain region to the body region; and
a drain select gate adjacent to the body region and the drain connecting region.
13. The memory device of claim 12 , wherein both the source connecting region and the drain connecting region are formed from the same material.
14. The memory device of claim 12 , wherein the drain connecting region comprises silicon germanium.
15. The memory device of claim 1 , wherein a gate induced drain leakage current in the body region during a boost operation of a string including the body region is low compared to a gate induced drain leakage current in the body region during an erase operation of the string including the body region.
16. The memory device of claim 1 , wherein the connecting region is located between the source region and the body region.
17. A memory device, comprising:
a memory cell string including:
a body region comprising a semiconductor having a first band gap, the body region having a first upward facing end and a second upward facing end;
a drain region coupled to the first upward facing end;
a source region coupled to the second upward facing end;
a plurality of gates along a length of the body region;
a connecting region comprising a semiconductor having a second band gap, the second band gap being lower than the first band gap, the connecting region coupling the source region to the body region;
a source select gate adjacent to the body region and the connecting region; and
a data line coupled to the drain region; and
a source line coupled to the source region.
18. The memory device of claim 17 , wherein the connecting region comprises silicon germanium.
19. The memory device of claim 17 , wherein the connecting region comprises Si x Ge 1-x where x is approximately 0.5.
20. The memory device of claim 17 , wherein the connecting region comprises epitaxial Si x Ge 1-x .
21. The memory device of claim 17 , wherein the body region comprises p-doped silicon.
22. The memory device of claim 17 , wherein the source region is shared with an adjacent memory cell string.
23. The memory device of claim 17 , wherein the memory cell string is substantially U shaped.
24. The memory device of claim 17 , wherein each of the gates is shared with an adjacent memory cell string.
25. The memory device of claim 17 , wherein each of the gates substantially surrounds a respective cross section of the body region.
26. The memory device of claim 17 , wherein the body region comprises an elongated body region.
27. The memory device of claim 17 , wherein a first portion of the gates are shared with a first adjacent memory cell string and wherein a second portion of the gates are shared with a second adjacent memory cell string.