Computer processor and method with short forward jump instruction inhibiting
A computer processor is provided which hides jump instructions, in particular condition jump instructions, from side-channels. The processor comprises a forward jump detector for detecting a forward jump instruction having a jump target location which lies ahead and a jump inhibitor for inhibiting an execution of the forward jump instruction. The computer processor is configured for executing at least one intermediate computer instruction located between the inhibited forward jump instruction and the jump target location. The processor further comprises a storage destination modifier for modifying the storage destination determined by the at least one intermediate computer instruction to suppress the effects of execution of intermediate instructions. Since the intermediate instruction is executed regardless of the forward jump instruction, the jump is hidden in a side-channel. Secret information, such as cryptographic keys, on which the forward jump may depend, is also hidden.
1. A computer processor configured for executing a sequence of computer instructions, the computer processor comprising
a jump handler configured to determine whether a jump instruction in the sequence of computer instructions is to be taken and whether the jump instruction is to be inhibited, the jump instruction determining a jump target location in the sequence of computer instructions;
execution circuitry configured for executing a computer instruction to obtain a data result;
a storage handler configured for storing the data result to a storage destination determined by the computer instruction;
a forward jump detector configured for determining whether the jump target location lies further in the sequence of computer instructions compared to a location in the sequence of computer instructions containing the jump instruction, and determining a jump condition based on a number of instructions ahead at which the jump target location lies;
a jump inhibitor configured for inhibiting an execution of the jump instruction in dependency on the forward jump detector detecting that the jump target location lies further in the sequence of computer instructions compared to the location in the sequence of computer instructions including the jump instruction, wherein the jump inhibitor inhibits execution of the jump instruction by blocking forwarding of a jump signal sent to the jump inhibitor by a jump determinator of the jump handler, wherein the jump handler detects that the jump instruction is a conditional jump instruction, and wherein the conditional jump instruction depends on secret information, and wherein jump inhibition is restricted to relative branches of processor architecture; and
a storage destination modifier configured for modifying the storage destination in response to the jump condition being satisfied by the number of instructions ahead at which the jump target location lies and for modifying a storage destination for intermediate computer instructions located in the sequence of computer instructions in between the jump instruction and the jump target location in response to inhibition of the jump instruction,
wherein each of the jump handler, the storage handler, the forward jump detector, the jump inhibitor and the storage destination modifier is a subroutine stored in a non-transitory memory as computer instructions executable by the computer processor, and wherein the computer instructions are executed by the computer processor to perform respectively recited, aforesaid functions corresponding to the jump handler, the storage handler, the forward jump detector, the jump inhibitor and the storage destination modifier.
2. The computer processor as in claim 1 , comprising a register file, wherein the storage destination determined by the computer instruction is a destination register in the register file, and wherein the storage destination for the intermediate computer instructions is modified in response to a determination that the number of instructions ahead at which the jump target location lies is less than eight instructions, wherein the jump handler is configured and arranged to not modify a program counter value in response to the inhibition of the execution of the jump instruction.
3. The computer processor as in claim 1 , wherein the forward jump detector is further configured for detecting whether a difference in location between the jump target location and a location of the jump instruction is less than a predetermined small jump threshold.
4. The computer processor as in claim 1 , wherein the jump inhibitor is further configured to inhibit execution of all further jump instructions being located in the sequence of computer instructions in between the inhibited jump instruction and the jump target location.
5. The computer processor as in claim 1 , wherein the jump inhibitor is further configured to inhibit interrupts occurring during execution of at least one intermediate computer instruction located in the sequence of computer instructions in between the inhibited jump instruction and the jump target location.
6. The computer processor as in claim 1 , wherein power consumption of a jump instruction is independent of its inhibition by the jump inhibitor.
7. The computer processor as in claim 1 , wherein the execution circuitry is configured for executing all intermediate computer instructions located in the sequence of computer instructions between the inhibited jump instruction and the jump target location.
8. A smart card comprising the computer processor as in claim 1 .
9. The computer processor as in claim 1 further comprising a kill register, wherein the kill register is set to a difference in location between the jump target location and the location of the jump instruction on inhibiting the jump instruction, wherein the execution circuitry is configured and arranged for decreasing the kill register value upon executing an intermediate computer instruction, wherein the kill register is zero when the computer processor reaches the jump target location.
10. The computer processor as in claim 1 , wherein the execution circuitry is further configured to:
execute at least one intermediate computer instruction located in the sequence of the computer instructions in between the inhibited jump instruction and the jump target location in response to inhibition of the execution of the jump instruction, and
modify a storage destination for the at least one intermediate instruction in response to the forward jump detector determining the jump condition based on the number of instructions ahead at which the jump target location lies being less than a predetermined small jump threshold.
11. A non-transitory computer readable medium having computer instructions stored thereon, wherein when executed by a computer processor, the computer instructions cause the computer processor to perform operations comprising:
determining whether a jump instruction in a sequence of computer instructions is to be taken and whether the jump instruction is to be inhibited, the jump instruction determining a jump target location in the sequence of computer instructions;
executing a computer instruction to obtain a data result, the computer instruction being located in the sequence of computer instructions between the jump instruction and the jump target location;
storing the data result to a storage destination determined by the computer instruction, wherein the storage destination is a destination address in a memory;
determining whether the jump target location lies further in the sequence of computer instructions compared to a location in the sequence of computer instructions containing the jump instruction, and determining a jump condition based on a number of instructions ahead at which the jump target location lies;
inhibiting an execution of the jump instruction in dependency on detecting that the jump target location lies further in the sequence of computer instructions compared to the location in the sequence of computer instructions including the jump instruction, wherein a jump inhibitor inhibits execution of the jump instruction by blocking forwarding of a jump signal sent to the jump inhibitor by a jump determinator of a jump handler, wherein the jump instruction depends on secret information, and wherein jump inhibition is restricted to relative branches of processor architecture; and
modifying the storage destination in response to the jump condition being satisfied by the number of instructions ahead at which the jump target location lies and modifying a storage destination for intermediate computer instructions located in the sequence of computer instructions in between the jump instruction and the jump target location in response to inhibition of the jump instruction.
12. A computer processor configured for executing a sequence of computer instructions, the computer processor comprising:
a jump handler configured to determine whether a jump instruction in the sequence of computer instructions is to be taken and whether the jump instruction is to be inhibited, the jump instruction determining a jump target location in the sequence of computer instructions;
a forward jump detector configured for determining whether the jump instruction in the sequence of computer instructions includes a forward jump by determining if the jump target location lies further in the sequence of computer instructions compared to a location in the sequence of computer instructions containing the jump instruction, and determining a jump condition based on a number of instructions ahead at which the jump target location lies;
a jump inhibitor configured for inhibiting an execution of the jump instruction responsive to the forward jump detector determining that the jump target location lies further in the sequence of computer instructions compared to the location in the sequence of computer instructions including the jump instruction, wherein the jump inhibitor inhibits execution of the jump instruction by blocking forwarding of a jump signal sent to the jump inhibitor by a jump determinator of the jump handler, wherein jump inhibition is restricted to relative branches of processor architecture, and wherein the jump instruction depends on secret information;
execution circuitry configured for executing the jump instruction responsive to the determination that the jump instruction includes the forward jump to the jump target location that lies further in the sequence of computer instructions and within a number of computer instructions and for executing a computer instruction to obtain a data result;
a storage handler configured for storing the data result to a storage destination determined by the computer instruction; and
a storage destination modifier configured for modifying the storage destination in response to the jump condition being satisfied by the number of instructions ahead at which the jump target location lies and for modifying a storage destination for intermediate computer instructions located in the sequence of computer instructions in between the jump instruction and the jump target location in response to inhibition of the jump instruction,
wherein each of the jump handler, the forward jump detector, the jump inhibitor, the storage handler, and the storage destination modifier is a subroutine stored in a non-transitory memory as computer instructions executable by the computer processor, and wherein the computer instructions are executed by the computer processor to perform respectively recited, aforesaid functions corresponding to the forward jump detector and the jump inhibitor.
13. The computer processor as in claim 12 , wherein the execution circuitry is further configured to:
cause execution of intermediate computer instructions located in the sequence of computer instructions in between the inhibited jump instruction and the jump target location in response to execution of the jump instruction.