Integrated circuit micro-module
One aspect of the present invention relates to an integrated circuit package that includes multiple layers of a planarizing, photo-imageable epoxy that are formed over a substrate. In some designs, the substrate is a silicon wafer. An integrated circuit is embedded in the epoxy. An antenna, which is electrically coupled to the active face of the integrated circuit through an interconnect layer, is formed over one of the epoxy layers. In various embodiments, at least some of the epoxy layers are positioned between the substrate and the antenna such that there is a distance of at least approximately 100 microns between the substrate and the antenna.
1. A method for packaging integrated circuits, the method comprising:
sequentially depositing layers of epoxy over a substrate to form a multiplicity of planarized layers of epoxy over the substrate, wherein the epoxy layers are deposited by spin coating;
photolithographically patterning at least one of the epoxy layers after the at least one of the epoxy layers is deposited and before the next epoxy layer is deposited;
forming an opening in the at least one of the epoxy layers after the at least one of the epoxy layers is patterned and before the next epoxy layer is deposited;
placing a first integrated circuit within an associated one of the openings, wherein the first integrated circuit has a plurality of I/O bond pads and at least one of the epoxy layers is deposited after the placement of the first integrated circuit to thereby cover the first integrated circuit;
forming at least one interconnect layer on one of the epoxy layers, the at least one interconnect layer including at least one conductive via;
forming a first antenna on at least one of the epoxy layers, wherein the first antenna is electrically coupled with the active face of the first integrated circuit through at least one of the interconnect layers; and
forming a plurality of microsystems on the substrate, each microsystem being formed substantially concurrently by said sequential depositing of layers of epoxy over the substrate, said photolithographic patterning, said forming of an opening in the at least one of the epoxy layers, said placing of the first integrated circuit, said forming of the at least one interconnect layer, and said forming of the first antenna are performed such that each microsystem includes at least one antenna, at least one integrated circuit and at least one interconnect layer.
2. A method as recited in claim 1 , wherein:
the substrate is formed from a semiconductor material; and
at least some of the epoxy layers are stacked between the first antenna and the substrate such that there is a distance of at least approximately 100 microns between the first antenna and the substrate.
3. A method as recited in claim 1 , further comprising, after the sequential depositon of the layers of epoxy, grinding away portions of the substrate to thin the substrate.
4. A method as recited in claim 1 , further comprising:
encapsulating the plurality of microsystems in a molding material to form a molded panel structure;
singulating the molded panel structure to form a corresponding plurality of integrated circuit packages, each integrated circuit package including at least one microsystem.
5. A method for packaging integrated circuits, the method comprising:
sequentially depositing layers of epoxy over a substrate to form a multiplicity of planarized layers of epoxy over the substrate, wherein the epoxy layers are deposited by spin coating;
photolithographically patterning at least one of the epoxy layers after the at least one of the epoxy layers is deposited and before the next epoxy layer is deposited;
forming an opening in the at least one of the epoxy layers after the at least one of the epoxy layers is patterned and before the next epoxy layer is deposited;
placing a first integrated circuit within an associated one of the openings, wherein the first integrated circuit has a plurality of I/O bond pads and at least one of the epoxy layers is deposited after the placement of the first integrated circuit to thereby cover the first integrated circuit;
forming at least one interconnect layer on one of the epoxy layers, the at least one interconnect layer including at least one conductive via; and
forming a first antenna on at least one of the epoxy layers, wherein the first antenna is electrically coupled with the active face of the first integrated circuit through at least one of the interconnect layers wherein forming the first antenna further comprises:
forming an opening in a first layer of the deposited layers of epoxy;
covering the first layer of the deposited layers of epoxy with a seed layer, such that the seed layer at least substantially covers bottoms and sidewalls of the opening in the first layer and a field of the first layer;
depositing a photoresist layer over the seed layer;
photolithographically patterning the deposited photoresist layer;
removing portions of the photoresist layer, thereby exposing portions of the seed layer; and
electroplating a conductive material onto the exposed portions of the seed layer, such that the conductive material accumulates substantially concurrently on the field of the first layer, the bottom and the sidewalls of the opening in the first layer, wherein the conductive material that accumulates on the field of the first layer helps form the first antenna and wherein the conductive material that accumulates in the opening of the first layer helps to form a conductive via that helps electrically couple the active face of the first integrated circuit with the first antenna.