Semiconductor device having three-dimensional transistor and manufacturing method thereof
View Patent ↗A semiconductor device includes a silicon pillar formed substantially perpendicular to a principal surface of a silicon substrate, a first impurity diffusion layer and a second impurity diffusion layer arranged below and above the silicon pillar, respectively, a gate electrode arranged to penetrate through the silicon pillar in a horizontal direction, a gate dielectric film arranged between the gate electrode and the silicon pillar, a back-gate electrode arranged adjacent to the silicon pillar, and a back-gate dielectric film arranged between the back-gate electrode and the silicon pillar.
1. A semiconductor device comprising:
a silicon pillar projecting to substantially perpendicular to a principal surface of a substrate;
a first impurity diffusion layer arranged a lower part of the silicon pillar;
a second impurity diffusion layer arranged an upper part of the silicon pillar;
a gate electrode that penetrates through the silicon pillar in a direction substantially parallel to the principal surface of the substrate;
a gate dielectric film arranged between the gate electrode and the silicon pillar;
a back-gate electrode arranged adjacent to the silicon pillar; and
a back-gate dielectric film arranged between the back-gate electrode and the silicon pillar.
2. The semiconductor device as claimed in claim 1 , further comprising a third impurity diffusion layer arranged in contact with a top of the second impurity diffusion layer, wherein
the first and second impurity diffusion layers have a first conductivity type, and
the third impurity diffusion layer has a second conductivity type.
3. The semiconductor device as claimed in claim 2 , wherein
the semiconductor device is a semiconductor memory device having a word line and a bit line that are mutually orthogonal and a back-gate line that is parallel to the word line,
the silicon pillar is formed in plural in matrix,
the gate electrode penetrates through the silicon pillars arranged in a word line direction to form the word line,
the back-gate electrode is arranged adjacent to the silicon pillars arranged in the word line direction to form the back-gate line, and
the third impurity diffusion layer is arranged commonly to the silicon pillars arranged in a bit line direction to form the bit line.
4. The semiconductor device as claimed in claim 1 , wherein the first and second impurity diffusion layers have a first conductivity type.
5. The semiconductor device as claimed in claim 4 , wherein
the semiconductor device is a semiconductor memory device using a word line and a bit line that are mutually orthogonal and a back-gate line that is parallel to the word line,
the silicon pillar is formed in plural in matrix,
the gate electrode penetrates through the silicon pillars arranged in a word line direction to form the word line,
the back-gate electrode is arranged adjacent to the silicon pillars arranged in the word line direction to form the back-gate line, and
the second impurity diffusion layer is arranged commonly to the silicon pillars arranged in a bit line direction to form the bit line.