Memory devices using a plurality of diodes as program selectors with at least one being a polysilicon diode
View Patent ↗Embodiments of programmable memory cells using a plurality of diodes as program selectors are disclosed for memory cells that can be programmed based on direction of current flow. These memory cells are MRAM, RRAM, CBRAM, or other memory cells that have a programmable resistive element coupled to the P-terminal of a first diode and to the N-terminal of a second diode. At least one of the diodes can be a polysilicon diode fabricated using standard CMOS processes. The polysilicon diode can be constructed by P+/N+ implants on a polysilicon substrate as a program selector.
1. A memory, comprising:
a plurality of memory cells, at least one of the memory cells comprising:
a memory element having a first end and a second end, the first end being coupled to a first supply voltage line;
a first diode having a first end doped with a first type of dopant and a second end doped with a second type of dopant, the first end having a first terminal, the second end having a second terminal, the first terminal being coupled to the second end of the memory element; and
a second diode having a first end doped with the first type of dopant and a second end doped with the second type of dopant, the first end having a first terminal, the second end having a second terminal, the second terminal being coupled to the second end of the memory element,
wherein the second terminal of the first diode coupled to a second supply voltage line,
wherein the first terminal of the second diode is coupled to the second supply voltage line or a third supply voltage line, and
wherein the memory element is configured to be programmable into one state by applying voltages to the first, second, and/or third supply voltage lines to conduct the first diode while cutting off the second diode, or into another state by applying voltages to the first, second, and/or third supply voltage lines to conduct the second diode while cutting off the first diode.
2. The memory as recited in claim 1 , wherein the memory element is a Magnetic Tunnel Junction (MTJ) that has a multi-layer of ferromagnetic or anti-ferromagnetic as a fixed-layer stack, another multi-layer of ferromagnetic or anti-ferromagnetic stack as a free-layer stack, and a dielectric layer in between the stacks.
3. The memory as recited in claim 2 , wherein the MTJ has an ellipse shape on the silicon surface.
4. The memory as recited in claim 2 , wherein the MTJ has a slant ellipse shape on the silicon surface with respect to the first or second supply voltage line.
5. The memory as recited in claim 1 , wherein the memory element comprises a metal-oxide film between metal or metal alloy electrodes.
6. The memory as recited in claim 1 , wherein the memory element comprises a solid-state electrolyte film between metal or metal alloy electrodes.
7. The memory as recited in claim 1 , wherein at least one of the diodes is built on a polysilicon structure.
8. The memory as recited in claim 1 , wherein the first and second diodes are built on a common polysilicon structure.
9. The memory as recited in claim 1 , wherein regions corresponding to the first and second ends are separated with a space that is covered by a silicide block layer that overlaps both the regions.
10. A memory, comprising:
a plurality of memory cells, at least one of the memory cells comprising:
a memory element having a first end and a second end, the first end being coupled to a first supply voltage line;
a first diode having a first end doped with a first type of dopant and a second end doped with a second type of dopant, the first end having a first terminal, the second end having a second terminal, the first terminal being coupled to the second end of the memory element; and
a second diode having a first end doped with the first type of dopant and a second end doped with the second type of dopant, the first end having a first terminal, the second end having a second terminal, the second terminal being coupled to the second end of the memory element,
wherein the second terminal of the first diode and the first terminal of the second diode are coupled to a second voltage line, and
wherein the memory element is configured to be programmable into one state by applying voltages to the first and second supply voltage lines to conduct the first diode while cutting off the second diode, and into another state by applying voltages to the first and second supply voltage lines to conduct the second diode while cutting off the first diode.
11. The memory as recited in claim 10 , wherein the memory element is a Magnetic Tunnel Junction (MTJ) that has a multi-layer of ferromagnetic or anti-ferromagnetic as a fixed-layer stack, another multi-layer of ferromagnetic or anti-ferromagnetic stack as a free-layer stack, and a dielectric layer in between the stacks.
12. The memory as recited in claim 10 , wherein the memory element comprises a metal-oxide film between metal or metal alloy electrodes.
13. The memory as recited in claim 10 , wherein the memory element comprises a solid-state electrolyte film between metal or metal alloy electrodes.
14. An electronics system, comprising:
a processor; and
a memory operatively connected to the processor, the memory including at least a plurality of memory cells, at least one of the memory cells comprising:
a memory element having a first end and a second end, the first end being coupled to a first supply voltage line;
a first diode having a first end doped with a first type of dopant and a second end doped with a second type of dopant, the first end having a first terminal, the second end having a second terminal, the first terminal coupled to the second end of the memory element, and the second terminal of the first diode being coupled to a second supply voltage line; and
a second diode having a first end doped with the first type of dopant and a second end doped with the second type of dopant, the first end having a first terminal, the second end having a second terminal, the second terminal coupled to the second end of the memory element, and the first terminal of the second diode being coupled to the second supply voltage line or a third supply voltage line,
wherein the memory element is configured to be programmable into one state by applying voltages to the first, second, and/or third supply voltage lines to conduct the first diode while cutting of the second diode in one current direction, and into another state by applying voltages to the first, second, and/or third supply voltage lines to conduct the second diode while cutting of the first diode in another current direction.
15. The electronics system as recited in claim 14 , wherein the memory element is a Magnetic Tunnel Junction (MTJ) that has a multi-layer of ferromagnetic or anti-ferromagnetic as a fixed layer stack, another multi-layer of ferromagnetic or anti-ferromagnetic stack as a free layer stack, and a dielectric layer in between the stacks.
16. The electronics system as recited in claim 15 , wherein the MTJ has an ellipse shape on the silicon surface.
17. The electronics system as recited in claim 15 , wherein the MTJ has a slant ellipse shape on the silicon surface with respect to the first or second supply voltage line.
18. The electronics system as recited in claim 14 , wherein the memory element comprises a metal-oxide film between metal or metal alloy electrodes.
19. The electronics system as recited in claim 14 , wherein the memory element comprises a solid-state electrolyte film between metal or metal alloy electrodes.
20. The electronics system as recited in claim 14 , wherein at least one of the diodes is built on a polysilicon structure.
21. The electronics system as recited in claim 14 , wherein the first and second diodes are built on a common polysilicon structure.
22. The electronics system as recited in claim 14 , wherein regions corresponding to the first and second ends are separated with a space that is covered by a silicide block layer that overlaps both the regions.
23. A method of operating a memory comprises:
providing a plurality of memory cells, at least one of the memory cells comprising:
a memory element having a first end coupled to a first supply voltage line;
a first diode having a first end doped with a first type of dopant and a second end doped with a second type of dopant, the first end having a first terminal, the second end having a second terminal, the first terminal being coupled to the second end of the memory element, the second terminal of the first diode being coupled to a second supply voltage line; and
a second diode having a first end doped with the first type of dopant and a second end doped with the second type of dopant, the first end having a first terminal, the second end having a second terminal, the second terminal being coupled to the second end of the memory element the first terminal of the second diode being coupled to the second supply voltage line or a third supply voltage line; and
applying voltages to the first, second, and/or third supply voltage lines to thereby change the memory element into one state by conducting the first diode while cutting off the second diode in one current direction, or into another state by conducting the second diode while cutting of the first diode in another current direction.