IP Library › Granted Patent US 8,338,287
Granted Patent B2
US 8,338,287 · App. 13/030,356 · Granted Dec 25, 2012

Semiconductor device and method for manufacturing the same

Assignee: Kabushiki Kaisha Toshiba
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Quick Facts
Patent No.
US 8,338,287
App. No.
13/030,356
Granted
Dec 25, 2012
Kind
B2
Abstract

In one embodiment, a preliminary solder layer made of a Sn alloy is formed on a connecting pad of a wiring substrate. A solder bump made of a Sn alloy is formed on an electrode pad of a semiconductor chip. After contacting the preliminary solder layer and the solder bump, the preliminary solder layer and the solder bump are melted by heating to a temperature of their melting points or higher to form a solder connecting part made of a Sn alloy containing Ag and Cu. Only the preliminary solder layer of the preliminary solder layer and the solder bump is composed of a Sn alloy containing Ag.

Claims (43)

1. A method for manufacturing a semiconductor device, comprising:

forming a preliminary solder layer made of a first Sn alloy containing Ag on a connecting pad of a wiring substrate;

forming a solder bump made of a second Sn alloy not containing Ag on an electrode pad of a semiconductor chip;

contacting the preliminary solder layer and the solder bump while aligning; and

melting the preliminary solder layer and the solder bump by heating to a temperature equal to or higher than melting points thereof to form a solder connecting part made of a third Sn alloy containing Ag and Cu and connect the connecting pad of the wiring substrate and the electrode pad of the semiconductor chip.

2. The method for manufacturing a semiconductor device according to claim 1 ,

wherein the preliminary solder layer is composed of a Sn—Ag alloy or a Sn—Ag—Cu alloy, and the solder bump is composed of a Sn—Cu alloy.

3. The method for manufacturing a semiconductor device according to claim 1 ,

wherein the preliminary solder layer is composed of the first Sn alloy consisting essentially of one of Ag in a range from 0.4 to 6 mass % and the balance of Sn, or Ag in a range from 0.4 to 6 mass %, Cu in a range from 0.4 to 6 mass % and the balance of Sn.

4. The method for manufacturing a semiconductor device according to claim 1 ,

wherein the solder bump is composed of the second Sn alloy consisting essentially of Cu in a range from 0.5 to 1 mass % and the balance of Sn.

5. The method for manufacturing a semiconductor device according to claim 1 ,

wherein the solder connecting part is composed of the third Sn alloy consisting essentially of Ag in a range from 0.2 to 1.5 mass %, Cu in a range from 0.3 to 1 mass % and the balance of Sn.

6. The method for manufacturing a semiconductor device according to claim 1 ,

wherein the solder bump is formed by stacked plating.

7. The method for manufacturing a semiconductor device according to claim 2 ,

wherein the solder bump is formed by stacking of Sn plating and Cu plating on the electrode pad.

8. The method for manufacturing a semiconductor device according to claim 2 ,

wherein the solder bump is formed by mounting a Sn—Cu alloy ball on the electrode pad.

9. The method for manufacturing a semiconductor device according to claim 1 ,

wherein the solder bump is formed on the electrode pad via a barrier metal layer.

10. A method for manufacturing a semiconductor device, comprising:

forming a preliminary solder layer made of a first Sn alloy containing Ag on a connecting pad of a wiring substrate via a first barrier metal layer;

forming a solder bump made of a second Sn alloy not containing Ag on an electrode pad of a semiconductor chip via a second barrier metal layer;

contacting the preliminary solder layer and the solder bump while aligning; and

melting the preliminary solder layer and the solder bump by heating to a temperature equal to or higher than melting points thereof to form a solder connecting part made of a third Sn alloy containing Ag and Cu and connect the connecting pad of the wiring substrate and the electrode pad of the semiconductor chip.

11. The method for manufacturing a semiconductor device according to claim 10 ,

wherein the preliminary solder layer is composed of a Sn—Ag alloy or a Sn—Ag—Cu alloy, and the solder bump is composed of a Sn—Cu alloy.

12. The method for manufacturing a semiconductor device according to claim 10 ,

wherein the preliminary solder layer is composed of the first Sn alloy consisting essentially of one of Ag in a range from 0.4 to 6 mass % and the balance of Sn, or Ag in a range from 0.4 to 6 mass %, Cu in a range from 0.5 to 1 mass % and the balance of Sn.

13. The method for manufacturing a semiconductor device according to claim 10 ,

wherein the solder bump is composed of the second Sn alloy consisting essentially of Cu in a range from 0.5 to 1 mass % and the balance of Sn.

14. The method for manufacturing a semiconductor device according to claim 10 ,

wherein at least one of the first barrier metal layer or the second barrier metal layer has a Ni film, and

wherein the solder connecting part is composed of the third Sn alloy consisting essentially of Ag in a range not less than 0.2 mass % and less than 1 mass %, Cu in a range from 0.3 to 1 mass % and the balance of Sn.

15. The method for manufacturing a semiconductor device according to claim 10 ,

wherein the first barrier metal layer has a Ni film and a Pd film disposed on a side closer to the preliminary solder layer than the Ni film, and

wherein the solder connecting part is composed of the third Sn alloy consisting essentially of Ag in a range from 0.2 to 1.5 mass %, Cu in a range from 0.3 to 1 mass % and the balance of Sn.

16. The method for manufacturing a semiconductor device according to claim 10 ,

wherein the second barrier metal layer has a Ni film and a Pd film disposed on a side closer to the solder bump than the Ni film, and

wherein the solder connecting part is composed of the third Sn alloy consisting essentially of Ag in a range from 0.2 to 1.5 mass %, Cu in a range from 0.3 to 1 mass % and the balance of Sn.

17. The method for manufacturing a semiconductor device according to claim 11 ,

wherein the solder bump is formed by stacking of Sn plating and Cu plating or by mounting a Sn—Cu alloy ball.

Assignments (5)
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 24, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043709/0035 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 18, 2011
From: MIURA, MASAYUKI; OYAMA, KATSUHIKO
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 025834/0911 →
Priority Claims (1)
JP P2010-068408 · Mar 24, 2010 · national
Continuity (1)
Related Publication 20110233793A1 · Sep 29, 2011