Use of emerging non-volatile memory elements with flash memory
View Patent ↗Memory devices and methods of operating memory devices are provided, such as those that involve a memory architecture that replaces typical static and/or dynamic components with emerging non-volatile memory (NV) elements. The emerging NV memory elements can replace conventional latches, can serve as a high speed interface between a flash memory array and external devices and can also be used as high performance cache memory for a flash memory array.
1. A memory device comprising:
an array of transistor-based non-volatile memory having emerging non-volatile memory for storing programming data into the array using sense circuitry.
2. The device of claim 1 , wherein the emerging non-volatile memory comprises phase change memory.
3. The device of claim 1 , wherein the emerging non-volatile memory comprises magnetoresistive memory.
4. The device of claim 1 , wherein the emerging non-volatile memory comprises resistive memory.
5. The device of claim 1 , wherein the emerging non-volatile memory comprises ferroelectric memory.
6. The device of claim 1 , wherein the emerging non-volatile memory comprises spin-transfer-torque memory.
7. The device of claim 1 , wherein the emerging non-volatile memory comprises nano-tube memory.
8. The device of claim 1 , wherein the array comprises a NAND flash memory array and is organized into a plurality of blocks having a block size, and wherein the emerging non-volatile memory is organized into at least one block having the block size.
9. The device of claim 1 , wherein bit lines of the emerging non-volatile memory connects to bit lines of the array of transistor-based non-volatile memory.
10. The device of claim 1 , wherein the emerging non-volatile memory stores blocks of data.
11. The device of claim 10 , wherein the emerging non-volatile memory stores blocks of data through the sense circuitry.
12. The device of claim 10 , wherein the blocks of data are used as cache memory.
13. A flash memory device comprising:
an array of first emerging non-volatile memory cells, the array being organized into a plurality of memory blocks, each memory block comprising a plurality of memory pages; and
a cache memory circuit electrically coupled to the array, the cache memory circuit comprising a second emerging non-volatile memory element for storing programming data in the array of first emerging non-volatile memory cells, wherein the second emerging non-volatile memory element being organized into at least one memory block.
14. The flash memory device of claim 13 , wherein the array and the cache memory circuit are in a same module.
15. The flash memory device of claim 13 , wherein the array and the cache memory circuit are on a same circuit board.
16. The flash memory device of claim 13 , wherein the cache memory circuit is stacked with the array in a same chip package.
17. A circuit comprising:
circuitry coupled to an array of first non-volatile memory elements, the circuitry comprising one second emerging non-volatile memory element and a sense circuit, wherein programming data from the one second emerging non-volatile memory element is stored in the array of first non-volatile memory elements via the sense circuit.
18. The circuit of claim 17 , wherein the array and the circuitry are in a same module.
19. The circuit of claim 17 , wherein the array and the circuitry are on a same circuit board.
20. The circuit of claim 17 , wherein the array is organized into a plurality of blocks having a block size, and wherein the one second emerging non-volatile memory element is organized into a block having the block size.
21. The circuit of claim 17 , wherein the one second emerging non-volatile memory element comprises a phase change memory element.
22. The circuit of claim 17 , wherein the one second emerging non-volatile memory element comprises a resistive memory element.
23. A method comprising:
storing data in a plurality of blocks of emerging non-volatile memory;
programming an array of non-volatile memory cells; and
mapping a defective set of memory blocks with the array of non-volatile memory cells and replacing them with the plurality of blocks of emerging non-volatile memory.
24. The method of claim 23 , further comprising the step of using the plurality of blocks of emerging non-volatile memory as redundant memory blocks.
25. A method comprising:
storing data in a plurality of blocks of emerging non-volatile memory;
programming array of non-volatile memory cells; and
performing a memory cleaning operation while the data is stored in the plurality of blocks of emerging non-volatile memory before it is programmed into the array of non-volatile memory cells.