Integrated circuit and method for controlling data output impedance
An integrated circuit for controlling data output impedance includes an address decoder, a selection signal decoder, and a transfer control unit. The address decoder is configured to decode an address signal and generate a selection mode signal and a first adjustment mode signal. The selection signal decoder is configured to decode a selection signal and generate an enable signal and a disable signal. The transfer control unit is configured to transfer a pull-up signal and a pull-down signal as a selection pull-up signal and a selection pull-down signal.
1. An integrated circuit for controlling data output impedance, the integrated circuit comprising:
an address decoder configured to decode an address signal and generate a selection mode signal and a first adjustment mode signal;
a selection signal decoder configured to decode a selection signal in response to the selection mode signal and generate an enable signal and a disable signal; and
a transfer control unit configured to transfer a pull-up signal and a pull-down signal as a selection pull-up signal and a selection pull-down signal in response to the enable signal,
wherein the selection pull-up signal and the selection pull-down signal are signals for driving a driver.
2. The integrated circuit of claim 1 , wherein the address signal is applied from a memory control circuit through an address pad unit.
3. The integrated circuit of claim 1 , wherein the selection signal is applied from a memory control circuit through a DQ pad unit in response to the selection mode signal.
4. The integrated circuit of claim 1 , further comprising a mode signal transfer unit configured to transfer the first adjustment mode signal as a second adjustment mode signal in response to the disable signal.
5. The integrated circuit of claim 4 , further comprising a control signal decoder configured to decode a control code in response to the second adjustment mode signal and generate the pull-up signal and the pull-down signal.
6. The integrated circuit of claim 5 , wherein the control code is applied from a memory control circuit through a DQ pad unit.
7. The integrated circuit of claim 1 , wherein the transfer control unit comprises:
a first transfer control section configured to transfer the pull-up signal and the pull-down signal as a first selection pull-up signal and a first selection pull-down signal in response to a first enable signal; and
a second transfer control section configured to transfer the pull-up signal and the pull-down signal as a second selection pull-up signal and a second selection pull-down signal in response to a second enable signal.
8. The integrated circuit of claim 7 , wherein the first selection pull-up signal and the first selection pull-down signal are set to a disabled state when the first enable signal is disabled, and the second selection pull-up signal and the second pull-down signal are set to a disabled state when the second enable signal is disabled.
9. The integrated circuit of claim 7 , further comprising:
a first OCD whose impedance is calibrated in response to the first selection pull-up signal and the first selection pull-down signal; and
a second OCD whose impedance is calibrated in response to the second selection pull-up signal and the second selection pull-down signal.
10. An integrated circuit for controlling data output impedance, the integrated circuit comprising:
A mode signal transfer unit configured to transfer a first adjustment mode signal generated by decoding of an address signal as a second adjustment mode signal in response to a disable signal;
A control signal decoder configured to decode a control code in response to the second adjustment mode signal and generate a pull-up signal and a pull-down signal; and
A transfer control unit configured to transfer the pull-up signal and the pull-down signal as a first selection pull-up signal and a first selection pull-down signal in response to a first enable signal to calibrate a impedance of a first OCD, and transfer the pull-up signal and the pull-down signal as a second selection pull-up signal and a second selection pull-down signal in response to a second enable signal to calibrate a impedance of a second OCD.
11. The integrated circuit of claim 10 , further comprising:
a selection signal decoder configured to decode a selection signal in response to a selection mode signal generated by decoding of the address signal, and generate the first and second enable signal and the disable signal.
12. A data output impedance control method comprising:
generating a selection mode signal by decoding an address signal having a first combination applied from a memory control circuit;
generating an enable signal and a disable signal by decoding a selection signal in response to the selection mode signal;
transferring a pull-up signal and a pull-down signal as a selection pull-up signal and a selection pull-down signal in response to the enable signal; and
driving a driver by using the selection pull-up signal and the selection pull-down signal.
13. The data output impedance control method of claim 12 , wherein the address signal is inputted through an address pad unit.
14. The data output impedance control method of claim 12 , wherein the selection signal is inputted from a memory control circuit through a DQ pad unit in response to the selection mode signal.
15. The data output impedance control method of claim 12 , further comprising generating a first adjustment mode signal by decoding an address signal having a second combination applied from the memory control circuit.
16. The data output impedance control method of claim 15 , further comprising transferring the first adjustment mode signal as a second adjustment mode signal in response to the enable signal.
17. The data output impedance control method of claim 16 , further comprising generating the pull-up signal and the pull-down signal by decoding a control code in response to the second adjustment mode signal.
18. The data output impedance control method of claim 17 , wherein the control code is inputted from a memory control circuit through a DQ pad unit including a plurality of DQ pads.
19. The data output impedance control method of claim 12 , wherein the pull-up signal and the pull-down signal are transferred as a first selection pull-up signal and a first selection pull-down signal in response to a first enable signal, and the pull-up signal and the pull-down signal are transferred as a second selection pull-up signal and a second selection pull-down signal in response to a second enable signal.
20. The data output impedance control method of claim 19 , wherein an impedance of a first OCD is controlled in response to the first selection pull-up signal and the first selection pull-down signal, and an impedance of a second OCD is controlled in response to the second selection pull-up signal and the second selection pull-down signal.