Supply independent current reference generator in CMOS technology
A current reference generator including a current network, a bias network, and a loop amplifier. The current network includes first and second transistors of a first conductivity type and third, fourth and fifth transistors of a second conductivity type. The first, third and fifth transistors are series-coupled between voltage supply lines forming a first current path, and the second and fourth transistors are series-coupled between the supply lines forming a second current path. The control terminals of the first and second transistors are coupled together and the control terminals of the third and fourth transistors are coupled together. The bias network biases the fifth transistor. The loop amplifier is coupled to the current network and is operative to maintain constant current level through the first and second current paths independent of voltage variations of the supply lines and at very low supply voltage.
1. A current reference generator, comprising:
a current network, comprising:
first and second transistors of a first conductivity type each having a first current terminal coupled to a first supply line and having a control terminal coupled to a first node, wherein said first transistor has a second current terminal coupled to a second node and wherein said second transistor has a second current terminal coupled to a third node;
a third transistor of a second conductivity type having a first current terminal coupled to said second node, having a control terminal coupled to a fourth node, and having a second current terminal coupled to a fifth node;
a fourth transistor of said second conductivity type having a first current terminal coupled to said third node, having a control terminal coupled to said fourth node, and having a second current terminal coupled to a second supply line;
a fifth transistor of said second conductivity type having a first current terminal coupled to said fifth node, having a second current terminal coupled to said second supply line, and having a control terminal; and
wherein said third transistor is diode-coupled in which said second and fourth nodes are coupled together;
a bias network coupled to at least one of said first and second supply lines and having a control output coupled to said control terminal of said fifth transistor; and
a loop amplifier having an input coupled to said third node and an output coupled to said first node, wherein said loop amplifier is operative to maintain relatively constant current level through said first, third and fifth transistors.
2. The current reference generator of claim 1 , wherein said loop amplifier comprises:
a voltage source providing a reference voltage indicative of said fourth node; and
an operational amplifier having an inverting input coupled to said third node, a non-inverting input receiving said reference voltage, and an output coupled to said first node.
3. The current reference generator of claim 1 , wherein said loop amplifier comprises:
a sixth transistor of said first conductivity type having a first current terminal coupled to said first supply line, and having a second current terminal and a control terminal both coupled to said first node; and
a seventh transistor of said second conductivity type having a first current terminal coupled to said first node, having a control terminal coupled to said third node, and having a second current terminal coupled to said second supply line.
4. The current reference generator of claim 3 , further comprising a capacitor coupled between said third node and said second supply line.
5. The current reference generator of claim 1 , further comprising a startup network coupled to initiate current through said first, third and fifth transistors.
6. The current reference generator of claim 5 , wherein said startup network comprises:
a sixth transistor of said second conductivity type having a first current terminal coupled to said first node, having a second current terminal coupled to said second supply line, and having a control terminal;
a seventh transistor of said second conductivity type having a first current terminal coupled to said control terminal of said sixth transistor, a control terminal coupled to said fourth node, and having a second current terminal coupled to said second supply line; and
a capacitor coupled between said first supply line and said control terminal of said sixth transistor.
7. The current reference generator of claim 1 , wherein said bias network comprises:
a sixth transistor of said first conductivity type having a control terminal coupled to said first node, having a first current terminal coupled to said first supply line and having a said second current terminal to said control terminal of said fifth transistor; and
a seventh transistor of said second conductivity type having a control terminal and a first current terminal both coupled to said control terminal of said fifth transistor, and having a second current terminal coupled to said second supply line.
8. The current reference generator of claim 1 , wherein said third, fourth and fifth transistors are sized to develop a voltage on said fifth node having a voltage level between voltages of said first and second supply lines.
9. The current reference generator of claim 1 , wherein said first conductivity type comprise one of P-type and N-type and wherein said second conductivity type comprises the other one of P-type and N-type.
10. The current reference generator of claim 1 , wherein each of said transistors of said first conductivity type comprises one of a PMOS transistor and an NMOS transistor and wherein each of said transistors of said second conductivity type comprises the other one of a PMOS transistor and an NMOS transistor.
11. The current reference generator of claim 1 , further comprising at least one output reference device coupled to said current network for mirroring current through said first and second current terminals of said fifth transistor.
12. A current reference generator, comprising:
a current network, comprising:
first and second transistors of a first conductivity type each having a first current terminal coupled to a first supply line and having a control terminal coupled to a first node, wherein said first transistor has a second current terminal coupled to a second node and wherein said second transistor has a second current terminal coupled to a third node;
a third transistor of a second conductivity type having a first current terminal coupled to said second node, having a control terminal coupled to a fourth node, and having a second current terminal coupled to a fifth node;
a fourth transistor of said second conductivity type having a first current terminal coupled to said third node, having a control terminal coupled to said fourth node, and having a second current terminal coupled to a second supply line;
a fifth transistor of said second conductivity type having a first current terminal coupled to said fifth node, having a second current terminal coupled to said second supply line, and having a control terminal; and
wherein said second transistor is diode-coupled in which said first and third nodes are coupled together;
a bias network coupled to at least one of said first and second supply lines and having a control output coupled to said control terminal of said fifth transistor; and
a loop amplifier having an input coupled to said second node and an output coupled to said fourth node, wherein said loop amplifier is operative to maintain relatively constant current level through said first, third and fifth transistors.
13. The current reference generator of claim 12 , wherein said loop amplifier comprises:
a voltage source providing a reference voltage indicative of said first node; and
an operational amplifier having an inverting input coupled to said second node, a non-inverting input receiving said reference voltage, and an output coupled to said fourth node.
14. The current reference generator of claim 12 , wherein said loop amplifier comprises:
a sixth transistor of said first conductivity type having a first current terminal coupled to said first supply line, having a second current terminal coupled to said fourth node, and having a control terminal coupled to said second node; and
a seventh transistor of said second conductivity type having a first current terminal and a control terminal both coupled to said fourth node, and having a second current terminal coupled to said second supply line.
15. The current reference generator of claim 14 , further comprising a capacitor coupled between said second node and said second supply line.
16. The current reference generator of claim 12 , further comprising a startup network coupled to initiate current through said first, third and fifth transistors.
17. The current reference generator of claim 16 , wherein said startup network comprises:
a sixth transistor of said second conductivity type having a first current terminal coupled to said first node, having a second current terminal coupled to said second supply line, and having a control terminal;
a seventh transistor of said second conductivity type having a first current terminal coupled to said control terminal of said sixth transistor, a control terminal coupled to said fourth node, and having a second current terminal coupled to said second supply line; and
a capacitor coupled between said first supply line and said control terminal of said sixth transistor.
18. The current reference generator of claim 12 , wherein said bias network comprises:
a sixth transistor of said first conductivity type having a control terminal coupled to said first node, having a first current terminal coupled to said first supply line and having a said second current terminal to said control terminal of said fifth transistor; and
a seventh transistor of said second conductivity type having a control terminal and a first current terminal both coupled to said control terminal of said fifth transistor, and having a second current terminal coupled to said second supply line.
19. The current reference generator of claim 12 , wherein said third, fourth and fifth transistors are sized to develop a voltage on said fifth node having a voltage level between voltages of said first and second supply lines.
20. The current reference generator of claim 12 , wherein said first conductivity type comprise one of P-type and N-type and wherein said second conductivity type comprises the other one of P-type and N-type.
21. The current reference generator of claim 12 , wherein each of said transistors of said first conductivity type comprises one of a PMOS transistor and an NMOS transistor and wherein each of said transistors of said second conductivity type comprises the other one of a PMOS transistor and an NMOS transistor.
22. The current reference generator of claim 12 , further comprising at least one output reference device coupled to said current network for mirroring current through said first and second current terminals of said fifth transistor.