CMP process flow for MEMS
The present invention generally relates to the formation of a micro-electromechanical system (MEMS) cantilever switch in a complementary metal oxide semiconductor (CMOS) back end of the line (BEOL) process. The cantilever switch is formed in electrical communication with a lower electrode in the structure. The lower electrode may be either blanket deposited and patterned or simply deposited in vias or trenches of the underlying structure. The excess material used for the lower electrode is then planarized by chemical mechanical polishing or planarization (CMP). The cantilever switch is then formed over the planarized lower electrode.
1. A method, comprising:
depositing one or more electrically conductive layers over a substrate, the substrate having a first dielectric layer with vias extending therethrough to underlying interconnect structures;
patterning the one or more electrically conductive layers to expose at least a portion of the first dielectric layer;
depositing a second dielectric layer over the patterned one or more electrically conductive layers and the exposed first dielectric layer;
chemical mechanical polishing the second dielectric layer and at least a portion of the patterned electrically conductive layers to create polished electrodes;
encapsulating the first dielectric layer and the polished electrodes; and
forming a cantilever device that is in electrical contact with at least a portion of the polished electrodes.
2. The method of claim 1 , wherein the one or more electrically conductive layers comprises a plurality of layers including:
a first conductive layer; and
a second conductive layer having a greater sheet resistance than the first conductive layer.
3. The method of claim 2 , wherein the first conductive layer comprises aluminum-copper and the second conductive layer comprises titanium nitride.
4. The method of claim 3 , wherein the first conductive layer is deposited to a thickness between about 5000 angstroms to about 9000 Angstroms and the second conductive layer is deposited to a thickness of between about 2000 Angstroms and about 3500 Angstroms.
5. The method of claim 1 , wherein the second dielectric layer comprises silicon dioxide.
6. The method of claim 1 , wherein the chemical mechanical polishing comprises removing between about 2000 Angstroms and about 3500 Angstroms of the one or more patterned electrically conductive layers.
7. The method of claim 1 , wherein the second dielectric layer comprises high density plasma deposited tetraethylorthosilicate.
8. The method of claim 1 , wherein depositing the second dielectric layer comprises depositing multiple dielectric layers.
9. The method of claim 8 , wherein the multiple dielectric layers comprise a HDP-SiO 2 layer and a PE-TEOS layer.
10. A method, comprising:
forming a plurality of vias through a dielectric layer formed above a substrate to expose one or more interconnect elements;
modifying one or more vias of the plurality of vias to form one or more trenches;
depositing one or more electrically conductive layers over the dielectric layer, over the exposed one or more interconnect elements, and within both the plurality of vias and the one or more trenches;
chemical mechanical polishing the one or more electrically conductive layers to expose at least a portion of the dielectric layer and to form MEMS electrodes;
encapsulating the dielectric layer and the MEMS electrodes; and
forming a cantilever device that is in electrical contact with at least one of the MEMS electrodes.
11. The method of claim 10 , wherein the one or more electrically conductive layers comprises a plurality of layers including:
one or more liner layers; and
a bulk layer.
12. The method of claim 11 , wherein the one or more liner layers comprise titanium and the bulk layer is selected from the group consisting of copper, tungsten, and combinations thereof.
13. The method of claim 12 , wherein the one or more liner layers comprise a titanium layer and a titanium nitride layer overlying the titanium layer.
14. The method of claim 10 , wherein at least one trench is disposed adjacent two vias that are separate from the at least one trench.
15. The method of claim 10 , wherein the cantilever device is spaced apart from the MEMS electrodes disposed within the one or more trenches.
16. The method of claim 15 , wherein the cantilever device is spaced apart from at least one MEMS electrode disposed within the plurality of vias.
17. A method, comprising:
forming one or more vias thorough a first dielectric layer to expose one or more interconnect elements;
forming one or more trenches within the first dielectric layer such that the one or more trenches and one or more vias are connected;
depositing one or more electrically conductive layers within the one or more vias with a first material, the one or more trenches, and over the first dielectric layer;
chemical mechanical polishing the one or more electrically conductive layers to expose the first dielectric layer and to form one or more MEMS electrodes within the one or more trenches;
encapsulating the first dielectric layer and the one or more MEMS electrodes; and
forming a cantilever device that is in electrical contact with the one or more MEMS electrodes.
18. The method of claim 17 , wherein the one or more electrically conductive layers comprises a plurality of layers including:
one or more liner layers; and
a bulk layer.
19. The method of claim 18 , wherein the one or more liner layers comprise titanium and the bulk layer is selected from the group consisting of copper, tungsten, and combinations thereof.
20. The method of claim 19 , wherein the one or more liner layers comprise a titanium layer and a titanium nitride layer overlying the titanium layer.