Manufacturing testing for LDPC codes
A storage system includes a channel detector, an LDPC decoder, and an erasure block. The channel detector is configured to receive data corresponding to data read from a storage and output an LLR signal. The LDPC decoder is configured to receive the LLR signal and output a feedback signal to the channel detector. The erasure block is configured to erase at a portion of at least one of the LLR signal and the feedback signal. A method for testing includes generating an error rate function corresponding to an erasure pattern. The function is a function of a number of LDPC iterations. The method includes determining testing parameters at least in part based on the error rate function, wherein the testing parameters comprise a testing number of LDPC iterations, a passing error rate, and the erasure pattern. The method includes testing storage devices using the testing parameters.
1. A system for testing storage devices, comprising:
a processor; and
a memory coupled with the processor, wherein the memory is configured to provide the processor with instructions which when executed cause the processor to:
generate an error rate function, wherein the error rate function is a function of a number of LDPC iterations, and wherein the error rate function corresponds to an erasure pattern;
determine a set of testing parameters at least in part based on the error rate function, wherein the set of testing parameters comprises a testing number of LDPC iterations, a passing error rate, and the erasure pattern; and
test one or more storage devices using the set of testing parameters.
2. The system of claim 1 , wherein generating the error rate function includes:
writing known data to a testing storage device;
reading the known data back from the testing storage device; and
causing the testing storage device to erase at least one of an LLR signal and a feedback signal according to the erasure pattern, wherein the LLR signal is received by a low-density parity-check (LDPC) decoder from a channel detector of the testing storage device, and wherein the feedback signal is received by the channel detector from the LDPC decoder.
3. The system of claim 2 , wherein generating the error rate function further includes:
comparing the data read back from the testing storage device with the known data.
4. The system of claim 2 , wherein erasing includes reducing the amplitude or zeroing out the at least one of the LLR signal and the feedback signal.
5. The system of claim 2 , wherein erasing comprises erasing in an evenly distributed erasure pattern.
6. The system of claim 2 , wherein erasing comprises erasing a window of the at least one of the LLR signal and the feedback signal.
7. The system of claim 1 , wherein determining the set of testing parameters is at least in part based on one or more of the following:
an estimate of a manufacturing yield;
an estimate of a failure parts per million value; and
an error rate margin.
8. A method for testing storage devices, comprising:
generating an error rate function by a processor, wherein the error rate function is a function of a number of LDPC iterations, and wherein the error rate function corresponds to an erasure pattern;
determining by the processor a set of testing parameters at least in part based on the error rate function, wherein the set of testing parameters comprises a testing number of LDPC iterations, a passing error rate, and the erasure pattern; and
testing one or more storage devices using the set of testing parameters.
9. The method of claim 8 , wherein generating the error rate function includes:
writing known data to a testing storage device;
reading the known data back from the testing storage device; and
causing the testing storage device to erase at least one of an LLR signal and a feedback signal according to the erasure pattern, wherein the LLR signal is received by a low-density parity-check (LDPC) decoder from a channel detector of the testing storage device, and wherein the feedback signal is received by the channel detector from the LDPC decoder.
10. The method of claim 9 , wherein generating the error rate function further includes:
comparing the data read back from the testing storage device with the known data.
11. The method of claim 9 , wherein erasing includes reducing the amplitude or zeroing out the at least one of the LLR signal and the feedback signal.
12. The method of claim 9 , wherein erasing comprises erasing in an evenly distributed erasure pattern.
13. The method of claim 9 , wherein erasing comprises erasing a window of the at least one of the LLR signal and the feedback signal.
14. The method of claim 8 , wherein determining the set of testing parameters is at least in part based on one or more of the following:
an estimate of a manufacturing yield;
an estimate of a failure parts per million value; and
an error rate margin.
15. A computer program product for testing a storage system, the computer program product being embodied in a non-transitory computer readable storage medium and comprising computer instructions for:
generating an error rate function, wherein the error rate function is a function of a number of LDPC iterations, and wherein the error rate function corresponds to an erasure pattern;
determining a set of testing parameters at least in part based on the error rate function, wherein the set of testing parameters comprises a testing number of LDPC iterations, a passing error rate, and the erasure pattern; and
testing one or more storage devices using the set of testing parameters.