3D semiconductor device
View Patent ↗A semiconductor device comprising first layer comprising multiplicity of first transistors and, second layer comprising multiplicity of second transistors and, at least one function constructed by the first transistors are structure so it could be replaced by a function constructed by the second transistors.
1. A semiconductor device comprising:
a first layer comprising a multiplicity of first transistors implementing a plurality of first combinatorial logic functions;
a second layer above or below the first layer comprising a multiplicity of second transistors implementing a plurality of second combinatorial logic functions;
each of said first combinatorial logic functions constructed by said first transistors is replaceable by at least one of said second combinatorial logic functions constructed by said second transistors; and
a plurality of connection paths between said first layer and said second layer,
wherein each of said connection paths comprise a through layer via,
wherein said through layer via has a radius of less than 200 nm, and
wherein said through layer via is through one of said first layer or said second layer.
2. The semiconductor device according to claim 1 ,
wherein said first layer comprises a plurality of flip-flops each having an input, and
wherein said input is selectively coupleable to at least one of said second transistors.
3. The semiconductor device according to claim 1 , further comprising:
a plurality of circuits each performing a comparison between a signal generated by the first transistors and a signal generated by the second transistors.
4. The semiconductor device according to claim 1 ,
wherein said first layer comprises a plurality of flip-flops each having an output, and
wherein said output is selectively coupleable to at least one of said second combinatorial logic functions.
5. The semiconductor device according to claim 1 , further comprising:
an interconnect layer disposed between said first layer and said second layer,
wherein said interconnect layer comprises copper or aluminum, and
wherein either said second transistors are lithographically aligned to said first transistors, or said first transistors are lithographically aligned to said second transistors.
6. A semiconductor device comprising:
a first layer comprising a multiplicity of first transistors implementing a plurality of first combinatorial logic functions;
a second layer above or below the first layer comprising a multiplicity of second transistors implementing a plurality of second combinatorial logic functions; and
each of said first combinatorial logic functions constructed by said first transistors is replaceable by at least one of said second combinatorial logic functions constructed by said second transistors,
wherein said first layer comprises a plurality of flip-flops each having an input, and
wherein said input is selectively coupleable to at least one of said second transistors.
7. The semiconductor device according to claim 6 , further comprising:
a plurality of connection paths between said first layer and said second layer,
wherein each of said connection paths comprise a through layer via,
wherein said through layer via has a radius of less than 200 nm, and
wherein said through layer via is through one of said first layer or said second layer.
8. The semiconductor device according to claim 6 , further comprising:
an interconnect layer disposed between said first layer and said second layer
wherein said interconnect layer comprises copper or aluminum, and
wherein either said second transistors are lithographically aligned to said first transistors, or said first transistors are lithographically aligned to said second transistors.
9. A semiconductor device comprising:
a first layer comprising a multiplicity of first transistors implementing a plurality of first combinatorial logic functions;
a second layer above or below the first layer comprising a multiplicity of second transistors implementing a plurality of second combinatorial logic functions; and
each of said first combinatorial logic functions constructed by said first transistors is replaceable by at least one of said second combinatorial logic functions constructed by said second transistors,
wherein said first layer comprises a plurality of flip-flops each having an output,
wherein said output is selectively coupleable to at least one of said second combinatorial logic functions.
10. The semiconductor device according to claim 9 , further comprising:
a plurality of connection paths between said first layer and said second layer,
wherein each of said connection paths comprise a through layer via,
wherein said through layer via has a radius of less than 200 nm, and
wherein said through layer via is through one of said first layer or said second layer.
11. The semiconductor device according to claim 9 , further comprising:
an interconnect layer disposed between said first layer and said second layer
wherein said interconnect layer comprises copper or aluminum, and
wherein either said second transistors are lithographically aligned to said first transistors, or said first transistors are lithographically aligned to said second transistors.
12. A semiconductor device comprising:
a first layer comprising a multiplicity of first transistors; and
a second layer comprising a multiplicity of second transistors,
wherein operation of said device is adapted to be repaired if non-functional by replacing a combinatorial logic or analog function constructed by said first transistors with a combinatorial logic or analog function constructed by said second transistors; and
a plurality of connection paths between said first layer and said second layer,
wherein each of said connection paths comprise a through layer via,
wherein said through layer via has a radius of less than 200 nm, and
wherein said through layer via is through one of said first layer or said second layer.
13. The semiconductor device according to claim 12 , further comprising:
an interconnect layer disposed between said first layer and said second layer
wherein said interconnect layer comprises copper or aluminum, and
wherein either said second transistors are lithographically aligned to said first transistors, or said first transistors are lithographically aligned to said second transistors.
14. A semiconductor device comprising:
a first layer comprising a multiplicity of first transistors; and
a second layer comprising a multiplicity of second transistors,
wherein operation of said device is adapted to be repaired if non-functional by replacing a combinatorial logic or analog function constructed by said first transistors with a combinatorial logic or analog function constructed by said second transistors; and
an interconnect layer disposed between said first layer and said second layer
wherein said interconnect layer comprises copper or aluminum, and
wherein either said second transistors are lithographically aligned to said first transistors, or said first transistors are lithographically aligned to said second transistors.
15. The semiconductor device according to claim 14 , further comprising:
a plurality of connection paths between said first layer and said second layer,
wherein each of said connection paths comprise a through layer via,
wherein said through layer via has a radius of less than 200 nm, and
wherein said through layer via is through one of said first layer or said second layer.
16. A semiconductor device comprising:
a first layer comprising a multiplicity of first transistors;
a second layer comprising a multiplicity of second transistors,
wherein operation of said device is adapted to be repaired if non-functional by replacing a combinatorial logic function constructed by said first transistors with a combinatorial logic function constructed by said second transistors; and
a plurality of connection paths between said first layer and said second layer,
wherein each of said connection paths comprise a through layer via,
wherein said through layer via has a radius of less than 200 nm, and
wherein said through layer via is through one of said first layer or said second layer.
17. The semiconductor device according to claim 16 ,
wherein said first layer comprises a plurality of flip-flops each having an input, and
wherein said input is selectively coupleable to at least one of said second transistors.
18. The semiconductor device according to claim 16 , further comprising:
a plurality of circuits each performing a comparison between a signal generated by the first transistors and a signal generated by the second transistors.
19. The semiconductor device according to claim 16 ,
wherein said first layer comprises a plurality of flip-flops each having an output, and
wherein said output is selectively coupleable to at least one of said combinatorial logic function constructed by said second transistors.
20. The semiconductor device according to claim 16 , further comprising:
an interconnect layer disposed between said first layer and said second layer,
wherein said interconnect layer comprises copper or aluminum, and
wherein either said second transistors are lithographically aligned to said first transistors, or said first transistors are lithographically aligned to said second transistors.