Secure Anti-Tamper Integrated Layer Security Device Comprising Nano-Structures
A device and method using one or more electrically conductive nano-structures defined on one or more surfaces of a microelectronic circuit such as an integrated circuit die, microelectronic circuit package a stacked microelectronic circuit package, or on the surface of one or more layers in a stack of layers containing one or more ICs. The nano-structure is in connection with a monitoring circuit and acts as a “trip wire” to detect unauthorized tampering with the device or module. Such a monitoring circuit may include a power source such as an in-circuit or in-module battery and a “zeroization” circuit within the chip or package to erase the contents of a memory when the nano-structure is breached or altered. One or more electrically conductive nano-structures interconnect and reroute one or more electrical connections between one or more ICs to create an “invisible” set of electrical connections on the chip or stack to obfuscate an attempt to reverse engineer the device. microscope.
1 . A tamper-resistant device comprising:
an electronic monitoring circuit comprising a stack of layers wherein the layers comprise at least one processing circuit and at least one memory circuit,
an electrically conductive nano-structure having a predetermined electrical characteristic in electrical connection with the electronic monitoring circuit, and,
the electronic monitoring circuit configured whereby a predetermined variance in the predetermined electrical characteristic initiates a predetermined response from the monitoring circuit.
2 . The device of claim 1 wherein the predetermined electrical characteristic comprises a predetermined electrical resistance.
3 . The device of claim 1 wherein the predetermined electrical characteristic comprises a predetermined electrical capacitance.
4 . The device of claim 1 wherein the predetermined electrical characteristic comprises a predetermined electrical inductance.
5 . The device of claim 1 comprising at least on active obfuscating component.
6 . The device of claim 1 wherein the predetermined response comprises disabling a circuit element by means of an overcurrent protection device.
7 . The device of claim 1 wherein the predetermined response comprises erasing the contents of a memory circuit.
8 . The device of claim 1 wherein the predetermined response comprises logically reconfiguring a first connection point in the device to a second connection point in the device.
9 . The device of claim 1 wherein at least one of the layers comprises a secure supervisor chip having non-imprinting memory for storing an encrypted key.