IP Library Granted Patent US 8,607,424
Granted Patent B1
US 8,607,424 · App. 13/046,640 · Granted Dec 17, 2013

Reverse MIM capacitor

Inventors: Vladimir Korobov (San Mateo, CA); Oliver Pohland (San Jose, CA)
Assignee: Cypress Semiconductor Corp.
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,607,424
App. No.
13/046,640
Granted
Dec 17, 2013
Kind
B1
Abstract

A method and apparatus for a reverse metal-insulator-metal (MIM) capacitor. The apparatus includes a lower metal layer, a bottom electrode, and an upper metal layer. The lower metal layer is disposed above a substrate layer. The bottom electrode is disposed above the lower metal layer and coupled to the lower metal layer. The upper metal layer is disposed above the bottom electrode. The upper metal layer comprises a top electrode of a metal-insulator-metal (MIM) capacitor.

Claims (11)

1. A method, comprising:

forming a lower metal layer above a substrate;

forming a bottom electrode of a metal-insulator-metal (MIM) capacitor above the lower metal layer;

forming a dielectric layer disposed between the lower metal layer and the bottom electrode;

forming a via extending from the lower metal layer to the bottom electrode;

forming an upper metal layer above the lower metal layer and the bottom electrode, wherein the upper metal layer comprises a top electrode of the MIM capacitor and a top metal layer of a pixel stack; and

defining an optical aperture in the pixel stack.

2. The method of claim 1 , wherein the upper metal layer comprises an intermediate metal layer of a pixel stack.

3. The method of claim 1 , further comprising forming a single intermediate layer between the lower metal layer and the upper metal layer, wherein the single intermediate layer comprises a second dielectric layer, wherein the top electrode of the upper metal layer is disposed above the second dielectric layer to prevent subsequent processing of the second dielectric layer.

4. The method of claim 3 , further comprising forming a spacer post adjacent to the bottom electrode and the dielectric layer.

5. The method of claim 1 , further comprising forming at least two intermediate layers between the lower metal layer and the upper metal layer, wherein the intermediate layers comprise at least the dielectric layer and an etch stop layer.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Mar 16, 2022
From: MUFG UNION BANK, N.A.
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 059410/0438 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 9, 2021
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MONTEREY RESEARCH, LLC
Reel/Frame 058346/0597 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 8, 2021
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MONTEREY RESEARCH, LLC
Reel/Frame 058340/0045 →
RELEASE OF SECURITY INTEREST Recorded Sep 14, 2021
From: MUFG UNION BANK, N.A.,
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 057501/0144 →
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Oct 28, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MUFG UNION BANK, N.A.
Reel/Frame 050896/0366 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 20, 2011
From: KOROBOV, VLADIMIR; POHLAND, OLIVER
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 026937/0793 →
Continuity (1)
Division 11644535 · Dec 22, 2006