Fully-depleted SON
A semiconductor device and a method of fabricating a semiconductor device. The semiconductor device includes a semiconductor substrate, an insulating layer, a first semiconductor layer, a dielectric layer, a second semiconductor layer, a source and drain junction, a gate, and a spacer. The method includes the steps of forming a semiconductor substrate, forming a shallow trench isolation layer, growing a first epitaxial layer, growing a second epitaxial layer, forming a gate, forming a spacer, performing a reactive ion etching, removing a portion of the first epitaxial layer, filling the void with a dielectric, etching back a portion of the dielectric, growing a silicon layer, implanting a source and drain junction, and forming an extension.
1. A method of fabricating a semiconductor device, said method comprising the steps of:
forming a shallow trench isolation layer around a semiconductor substrate;
growing a first epitaxial layer on said semiconductor substrate;
growing a second epitaxial layer on said first epitaxial layer;
forming a gate on said second epitaxial layer;
forming a spacer disposed around said gate and on said second epitaxial layer;
recessing said semiconductor substrate, first epitaxial layer and second epitaxial layer;
removing at least a portion of said first epitaxial layer to create a void between said substrate and said second epitaxial layer;
filling said void with a dielectric material;
etching back at least a portion of said dielectric material;
growing a semiconductor layer around said dielectric material;
forming a source and drain junction within said semiconductor layer; and
forming an extension to said gate wherein said extension is surrounded by said spacer.
2. The method of claim 1 , wherein the etching of the dielectric material creates a dielectric layer of about 3 nanometers to about 5 nanometers shorter than the length of the gate.
3. The method of claim 1 , wherein the first epitaxial layer is silicon-germanium.
4. The method of claim 1 , wherein the second epitaxial layer is silicon.
5. The method of claim 1 , further comprising the step of forming an implant for junction butting beneath the source and drain junction.
6. The method of claim 1 , wherein the dielectric material is a single-layer dielectric.
7. The method of claim 1 , wherein the dielectric material is a multi-layer dielectric.
8. The method of claim 1 , wherein the dielectric material has a thickness of about 10 nanometers to about 25 nanometers.
9. The method of claim 1 , wherein the first epitaxial layer and the second epitaxial layer are formed by chemical vapor deposition.
10. The method of claim 1 , wherein the first epitaxial layer is removed in a gas environment containing hydrogen chloride.
11. The method of claim 1 , wherein the recessing is performed by a reactive ion etching process.
12. The method of claim 1 , wherein the semiconductor layer has a thickness of about 2 nanometers to about 10 nanometers.