IP Library Granted Patent US 9,235,455
Granted Patent B2
US 9,235,455 · App. 13/049,604 · Granted Jan 12, 2016

Multi-core distributed processing using shared memory and communication link

Inventors: Danny S. Barnes (Maple Valley, WA); Serge H. Limondin (Milford, NH)
Assignee: Microscan Systems, Inc.
G06F9/544G06F9/54
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Quick Facts
Patent No.
US 9,235,455
App. No.
13/049,604
Granted
Jan 12, 2016
Kind
B2
Abstract

Embodiments of an apparatus including a first processor core having a local agent running thereon, the agent comprising a local process and a proxy agent and a second processor core having a remote agent running thereon, the remote agent being an instance of the local agent. A shared memory wherein coupled to the first processor core and the second processor core, wherein the local agent and the remote agent communicate via the shared memory. Other embodiments are disclosed and claimed.

Claims (52)

1. An apparatus comprising:

a first processor core running:

a local agent comprising a local process and a proxy agent, and

a local main transport process that instantiates a local transport agent, wherein the local transport agent communicates with the local main transport process, the proxy agent, and a remote transport agent;

a second processor core running:

a remote agent that is an instance of the local agent, and

a remote main transport process that instantiates the remote transport agent, wherein the remote transport agent is an instance of the local transport agent and communicates with the remote agent;

a memory coupled to the first processor core and the second processor core, wherein at runtime the local agent and the remote agent reads from and writes to the same block of memory addresses in the memory; and

a communication link between the first processor core and the second processor core, wherein the proxy agent instantiates the remote main transport process via the communication link, and wherein the remote transport agent instantiates the remote agent.

2. The apparatus of claim 1 wherein the communication link is a Multi-OS Inter-Process Communication (MIPC) transport.

3. The apparatus of claim 1 wherein the first processor core is different than the second processor core.

4. The apparatus of claim 3 wherein the first processor core is an Advanced RISC Machine (ARM) processor and the second processor core is a digital signal processor (DSP).

5. The apparatus of claim 1 wherein the first processor core has a local data management process running thereon, the second processor core has a remote data management process running thereon, and the local and remote data management processes manage data exchange via the same block of memory addresses in the memory.

6. The apparatus of claim 5 wherein the local and remote data management processes use re-directed pointer logic to manage data exchange via the same block of memory addresses in the memory.

7. The apparatus of claim 6 wherein the local and remote agents read from and write to the same block of memory addresses in the memory via the local and remote data management processes.

8. The apparatus of claim 5 wherein the first processor core includes a first cache whose cache coherency is managed by the local data management process and the second processor core includes a second cache whose cache coherency is managed by the remote data management process.

9. The apparatus of claim 1 wherein the memory is the exclusive runtime communication means between the first processor core and the second processor core.

10. The apparatus of claim 1 wherein the communication link comprises:

a first intra-core bus communicatively coupled to the first processor core;

a second intra-core bus communicatively coupled to the second processor core; and

an inter-core bus communicatively coupled to the first and second intra-core buses.

11. The apparatus of claim 10 wherein the local main transport process and the local transport agent are communicatively coupled to the first intra-core bus and the remote main transport process and the remote transport agent are communicatively coupled to the second intra-core bus.

12. The apparatus of claim 11 wherein the local transport agent can communicate with an agent port of the first intra-core bus and the local main transport process can communicate with a main port of the first intra-core bus.

13. The apparatus of claim 12 wherein the remote transport agent can communicate with an agent port of the second intra-core bus and the remote main transport process can communicate with a main port of the second intra-core bus.

14. The apparatus of claim 1 wherein the remote transport agent spawns a thread to instantiate the remote agent.

15. A process comprising:

on a first processor core, running:

a local agent comprising a local process and a proxy agent, and

a local main transport process that instantiates a local transport agent, wherein the local transport agent communicates with the local main transport process, the proxy agent, and a remote transport agent;

on a second processor core, constructing and running:

a remote agent that is an instance of the local agent, and

a remote main transport process that instantiates the remote transport agent, wherein the remote transport agent is an instance of the local transport agent and communicates with the remote agent;

communicating, at runtime, between the local agent and the remote agent via a block of memory addresses in a memory coupled to the first processor core and the second processor core; and

communicating using a communication link between the first processor core and the second processor core, wherein constructing the remote agent comprises using the proxy agent to instantiate the remote main transport process via the communication link, and using the remote transport agent to instantiate the remote agent.

16. The process of claim 15 wherein the communication link is a Multi-OS Inter-Process Communication (MIPC) transport.

17. The process of claim 15 wherein the first processor core is different than the second processor core.

18. The process of claim 17 wherein the first processor core is an Advanced RISC Machine (ARM) processor and the second processor core is a digital signal processor (DSP).

19. The process of claim 15 , further comprising:

running a local data management process on the first processor core; and

running a remote data management process on the second processor core, wherein the local and remote data management processes manage communication via the same block of memory addresses in the memory.

20. The process of claim 19 wherein the local and remote data management processes use re-directed pointer logic to communicate via the same block of memory addresses in the memory.

21. The process of claim 20 wherein the local and remote agents read from and write to the same block of memory addresses in the memory via the local and remote data management processes.

22. The process of claim 19 wherein the first processor core includes a first cache whose cache coherency is managed by the local data management process and the second processor core includes a second cache whose cache coherency is managed by the remote data management process.

23. The process of claim 15 wherein the memory is the exclusive runtime communication means between the first processor core and the second processor core.

24. The process of claim 15 wherein the communication link comprises:

a first intra-core bus communicatively coupled to the first processor core;

a second intra-core bus communicatively coupled to the second processor core; and

an inter-core bus communicatively coupled to the first and second intra-core buses.

25. The process of claim 24 wherein the local main transport process and the local transport agent are communicatively coupled to the first intra-core bus and the remote main transport process and the remote transport agent are communicatively coupled to the second intra-core bus.

26. The process of claim 25 wherein the local transport agent can communicate with an agent port of the first intra-core bus and the local main transport process can communicate with a main port of the first intra-core bus.

27. The process of claim 26 wherein the remote transport agent can communicate with an agent port of the second intra-core bus and the remote main transport process can communicate with a main port of the second intra-core bus.

28. The process of claim 15 wherein the remote transport agent spawns a thread to instantiate the remote agent.

Assignments (3)
CHANGE OF NAME Recorded Mar 6, 2019
From: MICROSCAN SYSTEMS INCORPORATED
To: OMRON MICROSCAN SYSTEMS, INC.
Reel/Frame 050244/0489 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 6, 2019
From: OMRON MICROSCAN SYSTEMS, INC.
To: OMRON CORPORATION
Reel/Frame 048524/0944 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 16, 2011
From: BARNES, DANNY S.; LIMONDIN, SERGE H.
To: MICROSCAN SYSTEMS, INC.
Reel/Frame 025970/0605 →
Continuity (1)
Related Publication 20120239905A1 · Sep 20, 2012