Method for reuse of wafers for growth of vertically-aligned wire arrays
Reusing a Si wafer for the formation of wire arrays by transferring the wire arrays to a polymer matrix, reusing a patterned oxide for several array growths, and finally polishing and reoxidizing the wafer surface and reapplying the patterned oxide.
1. A method for fabricating semiconductor structures comprising the steps of:
(a) forming a templated oxide layer on a substrate, wherein the templated oxide layer comprises openings in the oxide layer for the formation of semiconductor structures;
(b) depositing a catalyst in the openings in the oxide layer;
(c) growing a set of semiconductor structures on the substrate, wherein the semiconductor structure growth is supported by the catalyst deposited in the openings in the oxide layer;
(d) encapsulating the fabricated semiconductor structures in a binder material matrix;
(e) releasing the fabricated semiconductor structures from the substrate; and
(f) reusing the substrate for fabricating additional semiconductor structures by etching and cleaning the substrate and repeating steps (a) through (e).
2. The method according to claim 1 , further comprising conditioning the substrate after performing steps (a) through (e) and before performing step (f).
3. The method according to claim 1 , wherein encapsulating the fabricated semiconductor structures in a binder material matrix comprises depositing a film layer on a top surface of the templated oxide layer, wherein the film layer comprises the binder material matrix and wherein the film layer conformably fills gaps between grown semiconductor structures at and above the top surface of the oxide layer.
4. The method according to claim 3 , wherein releasing the fabricated semiconductor structures from the substrate comprises separating the film layer and the grown semiconductor structures from the oxide layer at or near a location where the film layer contacts a top surface of the oxide layer to provide a set of semiconductor structures embedded in the film layer.
5. The method according to claim 1 , wherein semiconductor structures comprise vertically aligned wire arrays.
6. The method according to claim 1 , wherein the binder material matrix comprises a polymer.
7. The method according to claim 1 , wherein the catalyst comprises gold, copper, nickel or some combination thereof.
8. The method according to claim 2 , wherein additionally conditioning the substrate comprises mechanically polishing the substrate.