Writing to asymmetric memory
View Patent ↗A memory controller writes to a virtual address associated with data residing within an asymmetric memory component of main memory that is within a computer system and that has a symmetric memory component, while preserving proximate other data residing within the asymmetric memory component. The symmetric memory component within the main memory of the computer system is configured to enable random access write operations in which an address within a block of the symmetric memory component is written without affecting the availability of other addresses within the block of the symmetric memory component during the writing of that address. The asymmetric memory component is configured to enable block write operations in which writing to an address within a region of the asymmetric memory component affects the availability of other addresses within the region of the asymmetric memory component during the block write operations involving the address.
1. A method of managing a memory system that has multiple parts including at least a first part of the memory system and a second part of the memory system, the first part of the memory system being different from the second part of the memory system in that the first part of the memory system has different access characteristics than the second part of the memory system or the first part of the memory system is used for a different type of memory-dependent operation than the second part of the memory system, the method comprising:
receiving a command from an application to write data to the memory system;
determining that the data is to be written to the second part of the memory system based on the command from the application;
despite determining that the data is to be written to the second part of the memory system based on the command from the application:
configuring a memory table to associate the data with a physical address within the first part of the memory system instead of the second part of the memory system,
writing the data to the physical address within the first part of the memory system, and
configuring a memory map to map the physical address within the first part of the memory system to which the data is written to a first virtual address;
receiving a first read request for the data;
determining, based on the memory map, that the first read request is associated with the first virtual address that is mapped to the physical address within the first part of the memory system; and
in satisfaction of the first read request, and based on determining that the first read request is associated with the first virtual address that is mapped to the physical address within the first part of the memory system, enabling access to the data at the physical address within the first part of the memory system.
2. The method of claim 1 , wherein the first part of the memory system is a symmetric memory component and the second part of the memory system is an asymmetric memory component.
3. The method of claim 1 , wherein the first part of the memory system is a volatile memory component and the second part of the memory system is a non-volatile memory component.
4. The method of claim 1 , wherein the first part of the memory system is a dynamic random access memory component and the second part of the memory system is a flash memory component.
5. The method of claim 1 , wherein the first part of the memory system has first absolute read and write speeds that are faster than second absolute read and write speeds of the second part of the memory system and a first difference between write speed and read speed of the first part of the memory system is less than a second difference between write speed and read speed of the second part of the memory system.
6. The method of claim 1 , wherein the first part of the memory system has different access characteristics than the second part of the memory system.
7. The method of claim 1 , wherein the first part of the memory system is used for a different type of memory-dependent operation than the second part of the memory system.
8. The method of claim 1 , wherein receiving the command from the application includes receiving a command to write to a second virtual address, further comprising:
detecting a write protection parameter for the second virtual address; and
using the write protection parameter to configure the memory table to associate the data with a physical address within the first part of the memory system instead of the second part of the memory system.
9. The method of claim 1 , further comprising:
configuring the memory table to associate, with physical addresses of the second part of the memory system, other data stored in a same page as the data and residing within the second part of the memory system;
determining that the data is to be written in the first part of the memory system based on a relationship between the data and the other data residing within the second part of the memory system;
writing the other data to the first part of the memory system;
configuring the memory map to map other virtual addresses associated with the other data to the first part of the memory system;
receiving a second read request;
determining, based on the memory map, that the second read request is associated with one or more of the other virtual addresses mapped by the memory map to corresponding addresses in the first part of the memory system; and
in satisfaction of the second read request and based on determining that the second read request is associated with one or more of the other virtual addresses mapped to the first part of the memory system, enabling access to the other data within the first part of the memory system.
10. The method of claim 1 , further comprising:
determining that the data has access characteristics more consistent with the second part of the memory system than the first part of the memory system; and
determining to write the data to the physical address within the first part of the memory system, despite determining that the data has access characteristics more consistent with the second part of the memory system than the first part of the memory system.
11. The method of claim 1 , further comprising:
maintaining, within an operating system, a page table that maps a virtual address accessed by the application with a physical address associated with either the first part of the memory system or the second part of the memory system;
receiving, on a central processing unit (CPU), the command from the application to write the data to the virtual address accessed by the application;
using the operating system to receive an allocation of memory from within the first part of the memory system;
using the operating system to write the data to the allocated memory from within the first part of the memory system; and
configuring the page table to associate the virtual address accessed by the application with a physical address for the allocated memory within the first part of the memory system.
12. The method of claim 1 , further comprising:
maintaining, using a hypervisor, a shadow page table that maps a virtual address accessed by the application with a physical address associated with either the first part of the memory system or the second part of the memory system;
receiving, on a CPU, the command to write the data associated with the virtual address accessed by the application;
inspecting an entry for the virtual address accessed by the application in the shadow page table;
detecting a write protection parameter associated with the virtual address accessed by the application;
identifying, using the hypervisor, an allocation of available memory in the first part of the memory system;
using the hypervisor to write the data to the allocated memory from within the first part of the memory system; and
configuring, within the hypervisor, the shadow page table to associate the virtual address accessed by the application with a physical address for the allocated memory within the first part of the memory system.
13. The method of claim 1 , further comprising:
receiving, from a CPU, a memory management unit-specified physical address that is processed by an intermediary component as the virtual address and is associated with the command to write;
providing the memory management unit-specified physical address to the memory map in the intermediary component;
using the memory map to determine that the memory management unit-specified physical address is associated with the second part of the memory system;
identifying, using the intermediary component, a physical address associated with available memory within the first part of the memory system;
associating, using the intermediary component, the physical address associated with the first part of the memory system with the memory management unit-specified physical address; and
writing, using the intermediary component, the data to the physical address associated with the first part of the memory system.
14. A system comprising:
a memory system that has multiple parts including at least a first part of the memory system that is different from a second part of the memory system in that the first part of the memory system has different access characteristics than the second part of the memory system or the first part of the memory system is used for a different type of memory-dependent operation than the second part of the memory system; and
a controller configured to perform operations comprising:
receiving a command from an application to write data to the memory system;
determining that the data is to be written to the second part of the memory system based on the command from the application;
despite determining that the data is to be written to the second part of the memory system based on the command from the application:
configuring a memory table to associate the data with a physical address within the first part of the memory system instead of the second part of the memory system,
writing the data to the physical address within the first part of the memory system, and
configuring a memory map to map the physical address within the first part of the memory system to which the data is written to a first virtual address;
receiving a first read request for the data;
determining, based on the memory map, that the first read request is associated with the first virtual address that is mapped to the physical address within the first part of the memory system; and
in satisfaction of the first read request, and based on determining that the first read request is associated with the first virtual address that is mapped to the physical address within the first part of the memory system, enabling access to the data at the physical address within the first part of the memory system.
15. The system of claim 14 , wherein the first part of the memory system is a symmetric memory component and the second part of the memory system is an asymmetric memory component.
16. The system of claim 14 , wherein the first part of the memory system is a volatile memory component and the second part of the memory system is a non-volatile memory component.
17. The system of claim 14 , wherein the first part of the memory system is a dynamic random access memory component and the second part of the memory system is a flash memory component.
18. The system of claim 14 , wherein the first part of the memory system has first absolute read and write speeds that are faster than second absolute read and write speeds of the second part of the memory system and a first difference between write speed and read speed of the first part of the memory system is less than a second difference between write speed and read speed of the second part of the memory system.
19. The system of claim 14 , wherein the first part of the memory system has different access characteristics than the second part of the memory system.
20. The system of claim 14 , wherein the first part of the memory system is used for a different type of memory-dependent operation than the second part of the memory system.