Clock hand-off circuit
View Patent ↗A second latch latches the output data of a first latch using a third clock having the same frequency as that of a first clock. A third latch latches the output data of the second latch using a second clock having a frequency N (N represents an integer) times that of the first clock and the third clock. The second clock and the third clock have a frequency division/multiplication relation therebetween.
1. A test apparatus comprising:
an oscillator configured to generate a first clock; and
a clock hand-off circuit configured to receive input data that is in synchronization with the first clock, and to hand off the input data to the second clock;
wherein the clock hand-off circuit comprises:
a first latch configured to latch input data using a first clock;
a frequency dividing circuit configured to divide a frequency of a second clock to generate a third clock, the frequency of the second clock being N times that of the first clock, where N represents an integer;
a second latch configured to latch output data of the first latch using the third clock;
a third latch configured to latch output data of the second latch using the second clock; and
a frequency multiplying circuit configured to generate the second clock by multiplying the frequency of the first clock by N;
wherein the phase of the third clock obtained by dividing the frequency of the second clock can be adjusted in increments of the period of the second clock.
2. A test apparatus comprising:
an oscillator configured to generate a first clock; and
a clock hand-off circuit configured to receive input data that is in synchronization with the first clock, and to hand off the input data to the second clock;
wherein the clock hand-off circuit comprises:
a first latch configured to latch input data using a first clock;
a frequency dividing circuit configured to divide a frequency of a second clock to generate a third clock, the frequency of the second clock being N times that of the first clock, where N represents an integer;
a second latch configured to latch output data of the first latch using the third clock;
a third latch configured to latch output data of the second latch using the second clock;
wherein the phase of the third clock obtained by dividing the frequency of the second clock can be adjusted in increments of the period of the second clock.
3. A clock hand-off circuit comprising:
a first latch configured to latch input data using a first clock;
a frequency dividing circuit configured to divide a frequency of a second clock to generate a third clock, the frequency of the second clock being N times that of the first clock, where N represents an integer:
a second latch configured to latch output data of the first latch using the third clock;
a third latch configured to latch output data of the second latch using the second clock; and
a frequency multiplying circuit configured to generate the second clock by multiplying the frequency of the first clock by N.
4. A clock hand-off circuit comprising:
a first latch configured to latch input data using a first clock;
a frequency dividing circuit configured to divide a frequency of a second clock to generate a third clock, the frequency of the second clock being N times that of the first clock, where N represents an integer;
a second latch configured to latch output data of the first latch using the third clock;
a third latch configured to latch output data of the second latch using the second clock;
wherein the phase of the third clock obtained by dividing the frequency of the second clock can be adjusted in increments of the period of the second clock.
5. The clock hand-off circuit according to claim 4 , further comprising a counter configured to count the time difference between an edge timing of the third clock and an edge timing of the output data of the first latch using the second clock.
6. The clock hand-off circuit according to claim 5 , wherein the phase of the third clock is adjusted such that the count value of the counter is within a predetermined range.
7. The clock hand-off circuit according to claim 6 , wherein the phase of the third clock is initialized by repeatedly performing a procedure while sweeping the phase of the third clock, the procedure comprising:
applying a predetermined pattern as the input data for each phase;
reading out the count value of the counter after the pattern is applied; and
judging whether or not the count value thus read out is within the predetermined range.
8. The clock hand-off circuit according to claim 6 , wherein the phase of the third clock is initialized by performing a procedure, the procedure comprising:
setting the phase of the third clock to a predetermined initial value;
applying a predetermined pattern as the input data for the phase thus set;
reading out the count value of the counter after the pattern is applied; and
setting the phase of the third clock to a first value that differs from the initial value when the count value thus read out is greater than an upper limit value of the predetermined range, and setting the phase of the third clock to a second value that differs from the initial value when the count value is smaller than a lower limit value of the predetermined range.
9. A test apparatus comprising:
an oscillator configured to generate a first clock; and
a clock hand-off circuit configured to receive input data that is in synchronization with the first clock, and to hand off the input data to the second clock;
wherein the clock hand-off circuit comprises:
a first latch configured to latch input data using a first clock;
a frequency dividing circuit configured to divide a frequency of a second clock to generate a third clock, the frequency of the second clock being N times that of the first clock, where N represents an integer;
a second latch configured to latch output data of the first latch using the third clock;
a third latch configured to latch output data of the second latch using the second clock; and
a frequency multiplying circuit configured to generate the second clock by multiplying the frequency of the first clock by N.
10. A clock hand-off circuit comprising:
a first latch configured to latch input data using a first clock;
a frequency dividing circuit configured to divide a frequency of a second clock to generate a third clock, the frequency of the second clock being N times that of the first clock, where N represents an integer;
a second latch configured to latch output data of the first latch using the third clock;
a third latch configured to latch output data of the second latch using the second clock; and
a frequency multiplying circuit configured to generate the second clock by multiplying the frequency of the first clock by N;
wherein the phase of the third clock obtained by dividing the frequency of the second clock can be adjusted in increments of the period of the second clock.
11. The clock hand-off circuit according to claim 10 , further comprising a counter configured to count the time difference between an edge timing of the third clock and an edge timing of the output data of the first latch using the second clock.
12. The clock hand-off circuit according to claim 11 , wherein the phase of the third clock is adjusted such that the count value of the counter is within a predetermined range.
13. The clock hand-off circuit according to claim 12 , wherein the phase of the third clock is initialized by repeatedly performing a procedure while sweeping the phase of the third clock, the procedure comprising:
applying a predetermined pattern as the input data for each phase;
reading out the count value of the counter after the pattern is applied; and
judging whether or not the count value thus read out is within the predetermined range.
14. The clock hand-off circuit according to claim 12 , wherein the phase of the third clock is initialized by performing a procedure, the procedure comprising:
setting the phase of the third clock to a predetermined initial value;
applying a predetermined pattern as the input data for the phase thus set;
reading out the count value of the counter after the pattern is applied; and
setting the phase of the third clock to a first value that differs from the initial value when the count value thus read out is greater than an upper limit value of the predetermined range, and setting the phase of the third clock to a second value that differs from the initial value when the count value is smaller than a lower limit value of the predetermined range.