Non-volatile resistance-switching thin film devices
Disclosed herein is a resistive switching device having an amorphous layer comprised of an insulating silicon-containing material and a conducting material. The amorphous layer may be disposed between two or more electrodes and be capable of switching between at least two resistance states. Circuits and memory devices including resistive switching devices are also disclosed, and a composition of matter involving an insulating silicon-containing material and a conducting material comprising between 5 and 40 percent by molar percentage of the composition is disclosed herein as well. Also disclosed herein are methods for switching the resistance of an amorphous material.
1. A resistive device, comprising:
an amorphous layer region that includes
an admixture composition of
an electrically conducting composition, and
an electrically insulating silicon-containing composition;
the electrically conducting composition comprising from about 5 percent to about 40 percent by molar percentage of the moles of electrically conducting composition and electrically insulating silicon-containing composition in the admixture composition,
wherein the electrically conducting composition comprises a metal M, wherein M comprises Pt, Pd, Ni, W, Au, Ag, Cu, Al, Rh, Re, Ir, Os, Ru, Nb, a conducting metal (Me) nitride, MeN x , a conducting metal (Me) silicide. MeSi x , or any combination thereof, wherein x is in the range of from about 0.5 to about 3;
the electrically insulating silicon-containing composition comprises a silicon-containing species SiO w N y wherein w is in the range of from 0 to about 2 and y is in the range of from 0 to about 4/3; and
wherein the molar percentage of the electrically conducting composition is defined as (%M+%Me)/(%M+%Me+%Si)x100%, wherein Si is from the electrically insulating silicon-containing composition, and
at least two electrodes in electrical contact with the amorphous layer region.
2. The resistive device of claim 1 , wherein the distance between the at least two electrodes is from about 4 to about 60 nanometers.
3. The resistive device of claim 1 , comprising a plurality of said amorphous layer regions.
4. The resistive device of claim 1 , wherein the electrically conducting composition comprises Pt.
5. The resistive device of claim 1 , wherein the conducting metal nitride comprises TiN, ZrN, HfN, NbN, TaN, or any combination thereof.
6. The resistive device of claim 1 , wherein the conducting metal silicide comprises PtSi 2 , TiSi 2 , CoSi 2 , NiSi 2 , NbSi 2 , TaSi 2 , MoSi 2 or WSi 2 , or any combination thereof.
7. The resistive device of claim 1 , wherein the electrically insulating silicon-containing composition comprises B or P doped silicon oxide.
8. The resistive device of claim 1 , wherein the electrically conducting composition comprises from about 6 percent to about 35 percent by molar percentage of the moles of electrically conducting composition and electrically insulating silicon-containing composition in the admixture composition.
9. The resistive device of claim 1 , wherein the electrically conducting composition comprises from about 7 percent to about 30 percent by molar percentage of the moles of electrically conducting composition and electrically insulating silicon-containing composition in the admixture composition.
10. The resistive device of claim 1 , wherein the electrically conducting composition comprises from about 8 percent to about 25 percent by molar percentage of the moles of electrically conducting composition and electrically insulating silicon-containing composition in the admixture composition.
11. The resistive device of claim 1 , wherein the amorphous layer region comprises less than five percent crystallites of the electrically conducting composition by weight of the moles of electrically conducting composition and electrically insulating silicon-containing composition in the admixture composition.
12. The resistive device of claim 1 , wherein the distance between the at least two electrodes is from about 5 to about 50 nanometers.
13. The resistive device of claim 1 , wherein the distance between the at least two electrodes is from about 6 to about 45 nanometers.
14. The resistive device of claim 1 , wherein the distance between the at least two electrodes is from about 7 to about 35 nanometers.
15. The resistive device of claim 1 , wherein the distance between the at least two electrodes is from about 8 to about 30 nanometers.
16. A circuit comprising a plurality of resistive devices, each one of which resistive devices comprises:
at least one amorphous layer, each amorphous layer comprising:
an admixture composition comprising
a composition comprising an electrically conducting composition, and
an electrically insulating silicon-containing composition;
the electrically conducting composition comprising from about 5 percent to about 40 percent by molar percentage of the moles of electrically conducting composition and electrically insulating silicon-containing composition in the admixture composition,
wherein the electrically conducting composition comprises a metal M, wherein M comprises Pt, Pd, Ni, W, Au, Ag, Cu, Al, Rh, Re, Ir, Os, Ru, Nb, a conducting metal (Me) nitride, MeN x , a conducting metal (Me) silicide, MeSi x , or any combination thereof, wherein x is in the range of from about 0.5 to about 3;
the electrically insulating silicon-containing composition comprises a silicon-containing species SiO w N y wherein w is in the range of from 0 to about 2, and y is in the range of from about 0 to about 4/3; and
wherein the molar percentage of the electrically conducting composition is defined as (%M+%Me)/(%M+%Me+%Si) x 100%, wherein Si is from the electrically insulating silicon-containing composition. and
at least two electrodes capable of being in electrical contact with a current source and with the amorphous layer.
17. The circuit of claim 16 , wherein the distance between the at least two electrodes is from about 4 to about 60 nanometers.
18. The circuit of claim 16 , comprising a plurality of said amorphous layers.
19. The circuit of claim 16 , wherein the electrically conducting composition is Pt.
20. The circuit of claim 16 , wherein the conducting metal nitride comprises TiN, ZrN, HfN, NbN or TaN.
21. The circuit of claim 16 , wherein the conducting metal silicide comprises PtSi 2 , TiSi 2 , CoSi 2 , NiSi 2 , NbSi 2 , TaSi 2 , MoSi 2 or WSi 2 , or any combination thereof.
22. The circuit of claim 16 , wherein the electrically insulating silicon-containing composition comprises B or P doped silicon oxide.
23. The circuit of claim 16 , wherein the electrically conducting composition comprises from about 6 percent to about 35 percent by molar percentage of the moles of electrically conducting composition and electrically insulating silicon-containing composition in the admixture composition.
24. The circuit of claim 16 , wherein the electrically conducting composition comprises from about 7 percent to about 30 percent by molar percentage of the moles of electrically conducting composition and electrically insulating silicon-containing composition in the admixture composition.
25. The circuit of claim 16 , wherein the electrically conducting composition comprises from about 8 percent to about 25 percent by molar percentage of the moles of electrically conducting composition and electrically insulating silicon-containing composition in the admixture composition.
26. The circuit of claim 16 , wherein the amorphous layer comprises less than five percent crystallites of the electrically conducting composition by weight of the moles of electrically conducting composition and electrically insulating silicon-containing composition in the admixture composition.
27. The circuit of claim 16 , wherein the distance between the at least two electrodes is from about 5 to about 50 nanometers.
28. The circuit of claim 16 , wherein the distance between the at least two electrodes is from about 6 to about 45 nanometers.
29. The circuit of claim 16 , wherein the distance between the at least two electrodes is from about 7 to about 35 nanometers.
30. The circuit of claim 16 , wherein the distance between the at least two electrodes is from about 8 to about 30 nanometers.
31. A memory device comprising one or more circuits, each circuit comprising:
at least one amorphous layer, the amorphous layer comprising
an admixture composition comprising
an electrically conducting composition, and
an electrically insulating silicon-containing composition;
the electrically conducting composition comprising from about 5 percent to about 40 percent by molar percentage of the moles of electrically conducting composition and electrically insulating silicon-containing composition in the admixture composition,
wherein the electrically conducting composition comprises a metal M, wherein M comprises Pt, Pd, Ni, W, Au, Ag, Cu, Al, Rh, Re, Ir, Os, Ru, Nb, a conducting metal (Me) nitride, MeN x a conducting metal (Me) silicide, MeSi x , or any combination thereof, wherein x is in the range of from about 0.5 to about 3;
the electrically insulating silicon-containing composition comprises a silicon-containing species SiO w N y , wherein w is in the range of from 0 to about 2, and y is in the range of from about 0 to about 4/3; and
wherein the molar percentage of the electrically conducting composition is defined as (%M+%Me)/(%M+%Me+%Si)x100%, wherein Si is from the electrically insulating silicon-containing composition,
and at least two electrodes in electrical contact with the amorphous layer.
32. The memory device of claim 31 , wherein the distance between the at least two electrodes is from about 4 to about 60 nanometers.
33. The memory device of claim 31 , comprising a plurality of said amorphous layers.
34. The circuit of claim 31 , wherein the electrically conducting composition is Pt.
35. The memory device of claim 31 , wherein the conducting metal nitride comprises TiN, ZrN, HfN, NbN or TaN.
36. The memory device of claim 31 , wherein the conducting metal silicide comprises PtSi 2 , TiSi 2 , CoSi 2 , NiSi 2 , NbSi 2 , TaSi 2 , MoSi 2 or WSi 2 , or any combination thereof.
37. The memory device of claim 31 , wherein the electrically insulating silicon-containing composition comprises B or P doped silicon oxide.
38. The memory device of claim 31 , wherein the electrically conducting composition comprises from about 6 percent to about 35 percent by molar percentage of the moles of electrically conducting composition and electrically insulating silicon-containing composition in the admixture composition.
39. The memory device of claim 31 , wherein the electrically conducting composition comprises from about 7 percent to about 30 percent by molar percentage of the moles of electrically conducting composition and electrically insulating silicon-containing composition in the admixture composition.
40. The memory device of claim 31 , wherein the electrically conducting composition comprises from about 8 percent to about 25 percent by molar percentage of the moles of electrically conducting composition and electrically insulating silicon-containing composition in the admixture composition.
41. The memory device of claim 31 , wherein the amorphous layer comprises less than five percent crystallites of the electrically conducting composition by weight of the moles of electrically conducting composition and electrically insulating silicon-containing composition in the admixture composition.
42. The memory device of claim 31 , wherein the distance between the at least two electrodes is from about 5 to about 50 nanometers.
43. The memory device of claim 31 , wherein the distance between the at least two electrodes is from about 6 to about 45 nanometers.
44. The memory device of claim 31 , wherein the distance between the at least two electrodes is from about 7 to about 35 nanometers.
45. The memory device of claim 31 , wherein the distance between the at least two electrodes is from about 8 to about 30 nanometers.