Semiconductor device and method for manufacturing the same

1. A semiconductor device comprising:

in a first region over a semiconductor substrate:

a first insulating layer located over the semiconductor substrate;

a first wiring embedded into the surface of the first insulating layer;

a second insulating layer located over the first insulating layer;

a third insulating layer located over the second insulating layer; and

a via and a second wiring embedded into the second insulating layer and the third insulating layer through a barrier metal and coupled to the first wiring, and

in a second region over the semiconductor substrate:

the first insulating layer located over the semiconductor substrate;

a gate electrode embedded into the surface of the first insulating layer;

the second insulating layer located over the first insulating layer;

a semiconductor layer located over the second insulating layer;

the third insulating layer located over the semiconductor layer; and

a first electric conductor and a second electric conductor embedded into the third insulating layer so as to sandwich the gate electrode in a position overlapped with the semiconductor layer in a plan view through a barrier metal and coupled to the semiconductor layer through the barrier metal.

2. The semiconductor device according to claim 1 ,

wherein at least one of a first contact region of the barrier metal contacting to the first electric conductor and the semiconductor layer and a second contact region of the barrier metal contacting to the second electric conductor and the semiconductor layer is not overlapped with the gate electrode in a plan view.

3. The semiconductor device according to claim 2 ,

wherein one of the first contact region and the second contact region is overlapped with the gate electrode in a plan view and the other is not overlapped with the gate electrode in a plan view.

4. The semiconductor device according to claim 1 ,

wherein the device comprises a plurality of the second regions;

wherein at least one of a first contact region of the barrier metal contacting to the first electric conductor and the semiconductor layer and a second contact region of the barrier metal contacting to the second electric conductor and the semiconductor layer are not overlapped with the gate electrode in a plan view in a primary second region; and

wherein both of the first contact region and the second contact region are overlapped with the gate electrode in a plan view in a secondary second region.

5. The semiconductor device according to claim 1 ,

wherein the semiconductor layer is an InGaZnO layer, an InZnO layer, a ZnO layer, ZnAlO layer or a ZnCuO layer.

6. The semiconductor device according to claim 1 ,

wherein a hard mask comprising one or more of SiN, SiO 2 and SiCOH is formed over the semiconductor layer; and

wherein the first electric conductor and the second electric conductor embedded through the barrier metal penetrates the hard mask.

7. The semiconductor device according to claim 6 ,

wherein the hard mask stacks two or more layers of a layer comprising SiN, a layer comprising SiO 2 , and a layer comprising SiCOH.

8. The semiconductor device according to claim 6 ,

wherein the hard mask and the semiconductor layer have approximately the same planar shape.

9. The semiconductor device according to claim 1 ,

wherein the barrier metal comprises one or more elements selected from a first group consisting of Ti, Ta, Ru and W.

10. The semiconductor device according to claim 1 ,

wherein the via, the second wiring, the first electric conductor and the second electric conductor are comprised of the same material.

11. The semiconductor device according to claim 10 ,

wherein the via, the second wiring, the first electric conductor and the second electric conductor comprise Cu; and

wherein the barrier metal comprises one or more elements selected from the first group consisting of Ti, Ta, Ru and W.

12. The semiconductor device according to claim 10 ,

wherein the via, the second wiring, the first electric conductor and the second electric conductor comprise Al; and

wherein the barrier metal comprises one or more elements selected from the first group consisting of Ti, Ta, Ru and W.

13. The semiconductor device according to claim 1 ,

wherein the gate electrode is embedded into the first insulating layer with contacting to the second insulating layer; and

wherein the first wiring and the gate electrode are comprised of the same material.

14. The semiconductor device according to claim 13 ,

wherein the first wiring and the gate electrode comprise Cu.

15. The semiconductor device according to claim 1 , further comprising:

an on-substrate element including an on-substrate gate electrode formed over the semiconductor substrate through a gate insulating film; and a source and a drain formed by doping impurity into the semiconductor substrate; and

wherein a first wiring layer element including the gate electrode, the second insulating layer, the semiconductor layer, the barrier metal, the first electric conductor and the second electric conductor formed in the second region, and the on-substrate element are electrically coupled.

16. The semiconductor device according to claim 15 ,

wherein the first wiring layer element has a function which acts as switching operation caused by a first signal inputted from the on-substrate element electrically coupled to the gate electrode of the first wiring layer element to the aforementioned gate electrode, and supplies higher voltage to a first device coupled to the first wiring layer element than the voltage of the first signal by the aforementioned switching operation.

17. The semiconductor device according to claim 16 ,

wherein the first electric conductor of the first wiring layer element is electrically coupled to a first voltage power source which supplies higher voltage than the voltage of the first signal; and

wherein the second electric conductor of the first wiring element is electrically coupled to the first device.

18. The semiconductor device according to claim 17 ,

wherein the first contact region of the barrier metal contacted to the first electric conductor and the semiconductor layer are not overlapped with the gate electrode in a plan view.

19. The semiconductor device according to claim 18 ,

wherein a second contact region of the barrier metal contacted to the second electric conductor and the semiconductor layer are overlapped with the gate electrode in a plan view.

20. The semiconductor device according to claim 15 , further comprising:

a second wiring layer element which acts as switching operation caused by a second signal inputted from a second device electrically coupled to the gate electrode of the second wiring layer element to the aforementioned gate electrode, and supplies lower voltage to the on-substrate element than the voltage of the second signal by the aforementioned switching operation.

21. The semiconductor device according to claim 20 ,

wherein a first electric conductor of the second wiring layer element is electrically coupled to a second voltage power source which supplies lower voltage than the voltage of the second signal; and

wherein the second electric conductor of the second wiring layer element is electrically coupled to the on-substrate element.