IP Library Granted Patent US 8,486,811
Granted Patent B2
US 8,486,811 · App. 13/067,584 · Granted Jul 16, 2013

Semiconductor device and manufacturing process therefor

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Quick Facts
Patent No.
US 8,486,811
App. No.
13/067,584
Granted
Jul 16, 2013
Kind
B2
Abstract

A process for manufacturing a semiconductor device, in which a current flows in a deflected part that includes a semiconductor, includes forming a straight beam having a doubly-clamped beam structure that includes the semiconductor by forming a void under the beam, filling the void with a liquid, and contacting a center of the beam with a bottom of the void by drying the liquid to form the deflected part.

Claims (22)

1. A process for manufacturing a Fin-type channel Field Effect Transistor (FinFET), said process comprising:

preparing a silicon on insulator (SOI) substrate in which a buried insulating film and a semiconductor layer are stacked on a substrate;

patterning the semiconductor layer to form a fin having a given width;

forming a void under the fin by etching the buried insulating film under the fin to provide a straight beam comprising a doubly-clamped beam structure;

filling the void with a liquid; and

contacting the fin with a bottom of the void by drying the liquid to deflect the fin,

wherein in contacting the fin with the bottom of the void, a center of the beam contacts with the bottom of the void.

2. A process for manufacturing a semiconductor device, in which a current flows in a deflected part that comprises a semiconductor, said process comprising:

forming a straight beam comprising a doubly-clamped beam structure that comprises the semiconductor by forming a void under the beam;

filling the void with a liquid;

contacting a center of the beam with a bottom of the void by drying the liquid to form the deflected part; and

forming a gate electrode in the deflected part,

wherein the gate electrode is devoid of having a doubly-clamped beam structure.

3. The process of claim 2 , wherein, in a width direction of the beam, edges of the beam are fixed and the center of the beam deflects.

4. The process of claim 3 , wherein, in the width direction of the beam, the center of the beam deflects to abut the bottom of the void.

5. The process of claim 2 , wherein the semiconductor device comprises a plurality of ones of said beam.

6. The process of claim 1 , further comprising:

forming a gate electrode in a deflected part of the fin,

wherein the gate electrode is devoid of having a doubly-clamped beam structure.

7. The process of claim 1 , wherein, in a width direction of the beam, edges of the fin are fixed and a central portion of the fin deflects.

8. The process of claim 7 , wherein, in the width direction of the fin, the central portion of the fin deflects to abut the bottom of the void.

9. The process of claim 1 , wherein the semiconductor device comprises a plurality of ones of said beam.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 28, 2015
From: NEC CORPORATION
To: GODO KAISHA IP BRIDGE 1
Reel/Frame 034834/0806 →