Calibration circuit, semiconductor device including the same, and data processing system

1. A method comprising:

issuing a calibration command; and

performing a calibration operation in response to the calibration command, the calibration operation comprising:

adjusting an impedance of a first replica buffer with updating a first code, the first replica buffer being substantially identical in circuit configuration to one of pull-up and pull-down circuits included in an output buffer;

adjusting an impedance of a second replica buffer with updating a second code, the second replica buffer being substantially identical in circuit configuration to the other of the pull-up and pull-down circuits included in the output buffer;

controlling a first latch circuit to hold the first code when the impedance of the first replica buffer reaches a first level; and

controlling a second latch circuit to hold the second code when the impedance of the second replica buffer reaches a second level.

2. The method as claimed in claim 1 , wherein, the first level is substantially equal to the second level.

3. The method as claimed in claim 1 , further comprising:

controlling the first latch circuit to hold the first code when a first period has been lapsed since issuance of the calibration command before the impedance of the first replica buffer reaches the first level.

4. The method as claimed in claim 3 , further comprising:

controlling the second latch circuit to hold the second code when a second period, that is longer than the first period, has been lapsed since the issuance of the calibration command before the impedance of the second replica buffer reaches the second level.

5. The method claimed in claim 4 , wherein the second period is substantially twice as long as the first period.

6. The method as claimed in claim 1 , wherein the updating of the first code is performed in a first operation mode and the updating of the second code is performed in a second operation mode.

7. The method as claimed in claim 6 , further comprising:

switching an operation mode from the first operation mode to the second operation mode when the impedance of the first replica buffer reaches the first level before the first period has been lapsed since the issuance of the calibration command.

8. A method comprising:

adjusting an impedance of a first replica buffer with updating a first code, the first replica buffer being substantially identical in circuit configuration to one of pull-up and pull-down circuits included in an output buffer;

adjusting an impedance of a second replica buffer with updating a second code, the second replica buffer being substantially identical in circuit configuration to the other of the pull-up and pull-down circuits included in the output buffer;

controlling a first latch circuit to hold the first code when the impedance of the first replica buffer reaches a first level; and

controlling a second latch circuit to hold the second code when the impedance of the second replica buffer reaches a second level.

9. The method as claimed in claim 8 , wherein the first level is substantially equal to the second level.

10. The method as claimed in claim 8 , further comprising:

controlling the first latch circuit to hold the first code when a first period has been lapsed since issuance of a calibration command before the impedance of the first replica buffer reaches the first level.

11. The method as claimed in claim 10 , further comprising:

controlling the second latch circuit to hold the second code when a second period, that is longer than the first period, has been lapsed since the issuance of the calibration command before the impedance of the second replica buffer reaches the second level.

12. The method as claimed in claim 11 , wherein the second period is substantially twice as long as the first period.

13. The method claimed in claim 8 , wherein the updating of the first code is performed in a first operation mode and the updating of the second code is performed in a second operation mode.

14. The method as claimed in claim 13 , further comprising:

switching an operation mode from the first operation mode to the second operation mode when the impedance of the first replica buffer reaches the first level before the first period has been lapsed since the issuance of the calibration command.

15. A system comprising:

a processor and a semiconductor device coupled to the processor issuing a calibration command, wherein the semiconductor device includes an output buffer and a calibration circuit adjusting impedances of a pull-up circuit and a pull-down circuit included in the output buffer, the calibration circuit comprising:

a first replica buffer substantially identical in circuit configuration to the pull-up circuit;

a second replica buffer substantially identical in circuit configuration to the pull-down circuit;

a counter circuit responding to the calibration command, and updating first and second codes defining impedances of the first and second replica buffers, respectively;

first and second latch circuits holding the first and second codes, respectively;

a first end-determining circuit activating the first latch circuit when impedance of the first replica buffer reaches a first level, and activating the second latch circuit when an impedance of the second replica buffer reaches a second level; and

a second end-determining circuit activating the first latch circuit when a first period has been lapsed since issuance of the calibration command and when the impedance of the first replica buffer has not reached the first level yet.

16. The system as claimed in claim 15 , wherein the second end-determining circuit activates the second latch circuit when a second period, that is longer than the first period, has been lapsed since the issuance of the calibration command before the impedance of the second replica buffer reaches the second level.

17. The system claimed in claim 15 , wherein the first level is substantially equal to the second level.

18. The system as claimed in claim 15 , wherein the counter circuit updates the first impedance code in a first operation mode and the second impedance code in a second operation mode.

19. The system as claimed in claim 16 , wherein the second period is substantially twice as long as the first period.

20. The system claimed in claim 18 , wherein the first end-determining circuit switches an operation mode from the first operation mode to the second operation mode when the impedance of the first replica buffer reaches the first level before the first period has been lapsed since the issuance of the calibration command.