IP Library Granted Patent US 8,558,285
Granted Patent B2
US 8,558,285 · App. 13/069,725 · Granted Oct 15, 2013

Method using low temperature wafer bonding to fabricate transistors with heterojunctions of Si(Ge) to III-N materials

Inventors: Umesh K. Mishra (Montecito, CA); Lee S. McCarthy (Santa Barbara, CA)
Assignee: The Regents of the University of California
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Quick Facts
Patent No.
US 8,558,285
App. No.
13/069,725
Granted
Oct 15, 2013
Kind
B2
Abstract

A method for fabricating an electronic device, comprising wafer bonding a first semiconductor material to a III-nitride semiconductor, at a temperature below 550° C., to form a device quality heterojunction between the first semiconductor material and the III-nitride semiconductor, wherein the first semiconductor material is different from the III-nitride semiconductor and is selected for superior properties, or preferred integration or fabrication characteristics in the injector region as compared to the III-nitride semiconductor.

Claims (33)

1. An electronic device, comprising:

a semiconductor material including an injector region;

a III-nitride material including a collector region or a drain region; and

a heterojunction formed between the semiconductor material and the III-nitride material, wherein the semiconductor material is not a III-nitride;

wherein the semiconductor material comprises a material stack including a Si layer and a SiGe layer and the SiGe layer is between the Si layer and the III-nitride material.

2. The device of claim 1 , wherein the III-nitride material is doped n-type.

3. The device of claim 1 wherein the device is a bipolar transistor.

4. The device of claim 1 , further comprising a bonded interface between the semiconductor material and the III-nitride material.

5. The device of claim 1 , wherein the semiconductor material has a different lattice constant, thermal properties, and crystalline structure as compared to the III-nitride material.

6. The device of claim 1 , wherein the device is a field effect transistor.

7. An electronic device, comprising:

a semiconductor material including an injector region;

a III-nitride material including a collector region or a drain region; and

a heterojunction formed between the semiconductor material and the III-nitride material,

wherein the semiconductor material is not a III-nitride and the semiconductor material includes a structure comprising n + -type Silicon (Si), p-type Si, and n-type Si and the n-type Si is adjacent to the III-nitride material.

8. The device of claim 7 , wherein the device is a field effect transistor.

9. A device, comprising:

a semiconductor material including an injector region;

a III-nitride material including a collector region or a drain region; and

a heterojunction formed between the semiconductor material and the III-nitride material, wherein the semiconductor material is not a III-nitride; and

an intermediate material region between the semiconductor material and the III-nitride material, the intermediate material region being selected from the group consisting of In, InP, a III-P compound, and a III-As compound.

10. The device of claim 9 , wherein the semiconductor material comprises a material stack including a Si layer and a SiGe layer.

11. The device of claim 10 , wherein the SiGe layer is between the Si layer and the III-nitride material.

12. The device of claim 10 , wherein the III-nitride material is doped n-type.

13. The device of claim 10 , wherein the device is a bipolar transistor.

14. The device of claim 9 , wherein the semiconductor material comprises silicon (Si).

15. The device of claim 9 , wherein the semiconductor material includes a structure comprising n + -type Silicon (Si), p-type Si, and n-type Si.

16. The device of claim 15 , wherein the n-type Si is adjacent to the III-nitride material.

17. The device of claim 9 , wherein the device is a field effect transistor.

18. The device of claim 9 , further comprising a bonded interface between the semiconductor material and the III-nitride material.

19. The device of claim 9 , wherein the semiconductor material has a different lattice constant as compared to the III-nitride material.

20. The device of claim 9 , wherein the semiconductor material has a different crystalline structure as compared to the III-nitride material.

21. The device of claim 9 , wherein the semiconductor material has different thermal properties as compared to the III-nitride material.

Assignments (1)
CONFIRMATORY LICENSE Recorded Nov 29, 2011
From: UNIVERSITY OF CALIFORNIA
To: UNITED STATES AIR FORCE
Reel/Frame 027389/0829 →
Continuity (3)
Continuation 12113847 · May 1, 2008
Provisional Application 60915334 · May 1, 2007
Related Publication 20110169050A1 · Jul 14, 2011