Data writing method and system
View Patent ↗A data writing method for writing data to a flash memory includes writing an initial value to the data storage area, determining whether or not the writing of the initial value is performed normally based on a write flag, writing data to the data storage area when the writing is performed normally, and erasing a block including the data storage area when the writing is not performed normally. An initial value is written to the data storage area before writing data, so that whether or not an error correction code storage area contains the initial value may be confirmed. An erase operation of the block is performed only when the error correction code storage area does not contain the initial value, so that the number of times of erasure of the block may be reduced and the life of the product may be increased.
1. A data writing method for writing data to a flash memory including a data storage area and an error correction code storage area, the method comprising:
writing an initial value to the data storage area;
determining, based on a write flag, whether or not the writing of the initial value is performed normally;
writing data to the data storage area when the writing is performed normally; and
erasing a block including the data storage area when the writing is not performed normally.
2. The data writing method according to claim 1 , wherein
N-bit wide data is written to the flash memory, N being a positive integer, and
one address is given to the data storage area having a 2N-bit width.
3. The data writing method according to claim 2 , wherein
based on data stored in the data storage area having the 2N-bit wide, an error correction code to be stored in the error correction code storage area corresponding to the data storage area is calculated.
4. The data writing method according to claim 1 , wherein
the N-bit wide data is written to the flash memory, N being a positive integer, and
the initial value has N bits.
5. The data writing method according to claim 4 , wherein
the N is 16 and the initial value is hexadecimal FFFF.
6. A system, comprising:
a CPU;
a flash memory including a data storage area and an error correction code storage area; and
a flash memory control circuit controlling the flash memory based on an instruction from the CPU, wherein
the flash memory control circuit:
performs writing of an initial value to the data storage area;
determines, based on a write flag, whether or not the writing of the initial value is performed normally;
writes data to the data storage area when the writing is performed normally; and
erases a block including the data storage area when the writing is not performed normally.
7. The system according to claim 6 , further comprising a data bus having an N-bit wide coupled between the flash memory and the flash memory control circuit, N being a positive integer, wherein
the flash memory control circuit writes data to the data storage area corresponding to one address via the data bus more than once.
8. The system according to claim 7 , wherein
the flash memory control circuit, based on data stored in the data storage area having the 2N-bit wide, calculates an error correction code to be stored in the error correction code storage area corresponding to the data storage area.
9. The system according to claim 6 , further comprising a data bus having an N-bit wide coupled between the flash memory and the flash memory control circuit, N being a positive integer, wherein
the initial value having N bits is written to the data storage area.
10. The system according to claim 9 , wherein
the N is 16 and the initial value is hexadecimal FFFF.