Method and system for providing automatic gate bias for field effect transistors

1. An RF amplifier circuit comprising:

FET for receiving a RF input signal and generating an amplified RF output signal, the FET having a gate, drain, and source;

control circuit, connected to the gate and drain of the FET, for controlling the current at the drain;

bias circuit comprising a means for biasing and variably compensating drift in the gate threshold voltage required to set the quiescent drain current, the bias circuit being connected to the control circuit and controlling operation of the control circuit to maintain an essentially constant drain current;

compensation means adapted to effect a change in drain current based at least in part on temperature variation to maintain essentially constant output power;

whereby the control circuit maintains essentially constant drain current with respect to time, input drive, frequency, and device-to-device variations, while allowing the compensation means to alter drain current with respect to temperature variations.

2. The circuit of claim 1 further comprising a sensing means, connected to the control circuit, for sensing change in temperature, and wherein the compensation means automatically adjusts the drain current based at least in part on temperature fluctuation to maintain essentially constant output power with respect to temperature throughout RF amplifier operation.

3. The circuit of claim 2 , wherein a thermistor comprises both the sensing means and the compensation means.

4. The circuit of claim 1 , further comprising:

detecting means, connected to the RF input signal, for detecting the power level of the RF input signal and supplying a DC voltage representative of the detected power level;

means for producing a variable reference voltage;

comparing means, having an input for receiving the variable reference voltage and being operably connected to the detecting means, for comparing the supplied DC voltage to the variable reference voltage; and

switching means, connected to the comparing means and the bias circuit, for turning off the FET based at least in part on a comparison of the supplied DC voltage and the variable reference voltage.

5. The circuit of claim 4 wherein disposed intermediate of the RF input signal and the detecting means is one or more of a group consisting of a capacitor and a coupler.

6. The circuit of claim 1 , further comprising:

detecting means, connected to the RF output signal of the circuit, for detecting the level of the output signal and supplying a DC voltage representative of the detected output signal level;

means for producing a variable reference voltage; and

adjusting means, operably connected to the detecting means, the variable reference voltage and the bias circuit, for automatically adjusting the drain current based at least in part on a comparison of the supplied DC voltage and the reference voltage to maintain essentially constant output RF power.

7. The circuit of claim 6 wherein disposed intermediate of the RF output signal and the detecting means is one or more of a group consisting of a capacitor and a coupler.

8. The circuit of claim 6 , further comprising:

digital reference voltage generator adapted to produce and output a digital signal representing the reference voltage; and

digital-to-analog convertor having an input for receiving the digital signal, and an output connected to the adjusting means for supplying a computer-controllable analog reference voltage signal to the adjusting means.

9. The circuit of claim 1 , further comprising:

first detecting means, connected to the RF input signal of the circuit, for detecting the power level of the input signal and supplying a first DC voltage representative of the detected input signal level;

second detecting means, connected to the RF output signal of the circuit, for detecting the level of the output signal and supplying a second DC voltage representative of the detected output signal level; and

adjusting means, connected to the first detecting means, the second detecting means and the bias circuit, for automatically adjusting the drain current based at least in part on a comparison of the second supplied DC voltage and the first supplied DC voltage by an amount necessary to maintain an essentially constant gain.

10. The circuit of claim 9 wherein disposed intermediate of the RF input signal and the detecting means is one or more of a group consisting of a first capacitor and a first coupler, and wherein disposed intermediate of the RF output signal and the detecting means is one or more of a group consisting of a second capacitor and a second coupler.

11. The circuit of claim 9 , further comprising a digital attenuator, connected to the RF input signal and the first detecting means, for adjusting a gain of the circuit.

12. The circuit of claim 1 , further comprising:

means for producing a negative voltage signal;

voltage regulator having an input and an output, the input operably connected to the negative voltage producing means and the drain of the FET, the output operably connected to the gate of the FET, the voltage regulator adapted to supply a regulated negative voltage signal to the gate of the FET; and

shutdown means, operably connected to the negative voltage producing means, for shutting down the negative voltage producing means after a wake-up transition;

whereby the voltage regulator supplies a regulated negative voltage signal to the gate of the FET both during and after the wake-up transition.

13. The circuit of claim 12 , wherein the voltage regulator comprises: an inverting amplifier comprising an operational amplifier, the negative supply of the operational amplifier being operably connected to the negative voltage producing means and the gate of the FET.

14. The circuit of claim 1 , wherein the biasing means comprises a variable resistance device adapted to selectively adjust the drain current independently of temperature variation.

15. The circuit of claim 1 , wherein the FET is one of a group consisting of LDFET, GaNFET, GaAsFET, JFET, and MOSFET.

16. A method comprising:

receiving by a FET a RF input signal and generating an amplified RF output signal, the FET having a gate, drain, and source;

controlling the current at the drain by biasing and variably compensating drift in the gate threshold voltage required to set the quiescent drain current to maintain an essentially constant current at the drain in connection with a wake-up transition; and

based at least in part on temperature change, automatically altering the drain current to maintain essentially constant output power with respect to temperature;

maintaining essentially constant drain current with respect to time, input drive, frequency, and device-to-device variations, while allowing a change in drain current with respect to temperature variations.

17. The method of claim 16 further comprising selectively adjusting the drain current independently of temperature change.

18. The method of claim 16 , further comprising:

detecting a power level of the RF input signal and supplying a DC voltage representative of the detected power level;

producing a variable reference voltage;

comparing the supplied DC voltage to the variable reference voltage; and

turning off the FET based at least in part on the comparing step.

19. The method of claim 16 , further comprising:

detecting the power level of the output signal and supplying a DC voltage representative of the detected output power level;

producing a variable reference voltage; and

automatically adjusting the drain current based at least in part on a comparison of the supplied DC voltage and the reference voltage to maintain essentially constant output RF power.

20. The method of claim 16 , further comprising:

detecting the power level of the input signal and supplying a first DC voltage representative of the detected input power level;

detecting the power level of the output signal and supplying a second DC voltage representative of the detected output power level; and

automatically adjusting the drain current based at least in part on a comparison of the second supplied DC voltage and the first supplied DC voltage by an amount necessary to maintain an essentially constant gain.

21. The method of claim 16 , further comprising:

producing a negative voltage signal;

supplying a regulated negative voltage signal to the gate of the FET;

shutting down the negative voltage producing means after a wake-up transition; and

supplying a regulated negative voltage signal to the gate of the FET both during and after the wake-up transition.