Metal gate transistor and resistor and method for fabricating the same
View Patent ↗A method for fabricating metal gate transistor and resistor is disclosed. The method includes the steps of: providing a substrate having a transistor region and a resistor region; forming a shallow trench isolation in the substrate of the resistor region; forming a tank in the shallow trench isolation of the resistor region; forming at least one gate in the transistor region and a resistor in the tank of the resistor region; and transforming the gate into a metal gate transistor.
1. A method for fabricating metal gate transistor and resistor, comprising:
providing a substrate having a transistor region and a resistor region;
forming a shallow trench isolation in the substrate of the resistor region;
forming a tank in the shallow trench isolation of the resistor region;
forming at least one gate in the transistor region and a resistor in the tank of the resistor region; and
transforming the gate into a metal gate transistor.
2. The method of claim 1 , further comprising forming a stacked film on surface of the substrate to cover the transistor region and the resistor region before forming the tank.
3. The method of claim 2 , wherein the stacked film comprises a high-k dielectric layer, a cap layer, and a metal layer.
4. The method of claim 2 , further comprising removing a portion of the shallow trench isolation and a portion of the stacked film of the resistor region for forming the tank.
5. The method of claim 2 , wherein after forming the tank further comprises:
forming a polysilicon layer on the tank of the resistor region and the stacked film of the transistor region;
forming a hard mask on the polysilicon layer; and
removing a portion of the hard mask, a portion of the polysilicon layer, and a portion of the stacked film to form the gate in the transistor region and the resistor in the tank of the resistor region.
6. The method of claim 5 , further comprising performing an etching process after forming the gate and the resistor for removing the remaining hard mask from surface of the resistor.
7. The method of claim 5 , wherein after forming the gate and the resistor further comprises:
forming a salicide block on the gate and the resistor;
performing an etching process for simultaneously removing the salicide block on the resistor and the remaining hard mask on surface of the resistor.
8. The method of claim 5 , wherein after forming the gate and the resistor further comprises:
forming a dielectric layer on the gate and the resistor;
performing a planarizing process for remove a portion of the dielectric layer until reaching the top of the gate;
removing the gate from the transistor region to expose the surface of the stacked film; and
forming a conductive layer on the dielectric layer and the stacked film for forming the metal gate transistor with metal gate in the transistor region.
9. The method of claim 8 , wherein after performing the planarizing process further comprises:
removing the gate from the transistor region and forming a plurality of openings in the dielectric layer of the resistor region to expose the surface of the shallow trench isolation; and
depositing a conductive material in the openings for forming a plurality of dummy conductive patterns.
10. The method of claim 8 , further comprising forming an interlayer dielectric layer on the dielectric layer for covering the metal gate transistor.
11. The method of claim 10 , further comprising forming a plurality of contact plugs in the interlayer dielectric layer and the dielectric layer for connecting the resistor and the metal gate transistor.
12. The method of claim 5 , wherein after forming the polysilicon layer further comprises performing a patterning process to form the resistor a plurality of dummy polysilicon pattern on surface of the tank.