IP Library Granted Patent US 8,319,346
Granted Patent B2
US 8,319,346 · App. 13/074,279 · Granted Nov 27, 2012

Semiconductor structure and manufacturing method of semiconductor structure

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Quick Facts
Patent No.
US 8,319,346
App. No.
13/074,279
Granted
Nov 27, 2012
Kind
B2
Abstract

Disclosed is a semiconductor structure including a semiconductor substrate including an electronic circuit which is provided in a predetermined region of the semiconductor substrate; a wall which is formed to encircle the predetermined region of the semiconductor substrate; a wiring provided in a region of the semiconductor substrate outside of the predetermined region of the semiconductor substrate; an external connection electrode provided on the wiring; a sealing resin which seals the wiring, the sealing resin being filled in the region of the semiconductor substrate outside of the wall; and a transparent resin to seal the predetermined region of the semiconductor substrate, the transparent resin being filled inside of the wall.

Claims (15)

1. A semiconductor structure, comprising:

a semiconductor substrate including an electronic circuit which is provided in a predetermined region of the semiconductor substrate;

a wall which is formed to encircle the predetermined region of the semiconductor substrate;

a wiring provided in a region of the semiconductor substrate outside of the predetermined region of the semiconductor substrate;

an external connection electrode provided on the wiring;

a sealing resin which seals the wiring, the sealing resin being filled in a region of the semiconductor substrate outside of the wall; and

a transparent resin to seal the predetermined region of the semiconductor substrate, the transparent resin being filled inside of the wall;

wherein the wall and the external connection electrode are formed of a same material.

2. The semiconductor structure according to claim 1 , wherein the wall and the external connection electrode have a same height level.

3. The semiconductor structure according to claim 1 , wherein a protective insulating film intervenes between the wall and the semiconductor substrate.

4. The semiconductor structure according to claim 1 , wherein the wall is grounded.

5. The semiconductor structure according to claim 4 , wherein the semiconductor substrate includes a connection pad for grounding and the connection pad for grounding is connected to the wall via a wiring for grounding.

6. The semiconductor structure according to claim 1 , wherein the external connection electrode is connected with an external circuit board.

7. The semiconductor structure according to claim 6 , wherein a solder terminal is provided between the external connection electrode and the external circuit board.

8. The semiconductor structure according to claim 6 , wherein a part of the external circuit board corresponding to the predetermined region of the semiconductor substrate forms an opening.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 27, 2017
From: TERA PROBE, INC.
To: AOI ELECTRONICS CO., LTD.
Reel/Frame 041521/0001 →
MERGER Recorded Jan 27, 2017
From: TERAMIKROS, INC.
To: TERA PROBE, INC.
Reel/Frame 041664/0471 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 7, 2011
From: CASIO COMPUTER CO., LTD.
To: TERAMIKROS, INC.
Reel/Frame 027342/0990 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 29, 2011
From: WAKISAKA, SHINJI
To: CASIO COMPUTER CO., LTD.
Reel/Frame 026040/0793 →