IP Library Granted Patent US 8,645,612
Granted Patent B2
US 8,645,612 · App. 13/076,952 · Granted Feb 4, 2014

Information processing device and information processing method

Inventors: Atsushi Kunimatsu (Funabashi, JP); Goh Uemura (Kawasaki, JP); Tsutomu Owa (Kawasaki, JP)
Assignee: Kabushiki Kaisha Toshiba
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Quick Facts
Patent No.
US 8,645,612
App. No.
13/076,952
Granted
Feb 4, 2014
Kind
B2
Abstract

According to one embodiment, an information processing device includes an OS and a virtual machine switching section. The OS accesses a hardware resource including a nonvolatile semiconductor memory and a semiconductor memory used as a cache memory of the nonvolatile semiconductor memory. The virtual machine switching section switches a virtual machine in exection from a first virtual machine to a second virtual machine while a cache process is executed, when cache miss in a process executed by the first virtual machine is detected.

Claims (44)

1. An information processing device comprising:

an operating system which accesses a hardware resource including a nonvolatile semiconductor memory and a semiconductor memory used as a cache memory of the nonvolatile semiconductor memory;

first and second virtual machines operating on the operating system;

a cache-miss detection section which detects cache miss to the semiconductor memory in a process executed by the first virtual machine;

a cache control section which executes a cache process when the cache-miss detection section detects the cache miss in the process; and

a virtual machine switching section which, when the cache-miss detection section detects the cache miss in the process executed by the first virtual machine, switches a virtual machine in execution from the first virtual machine to the second virtual machine while the cache control section executes the cache process,

wherein the operating system selects process switching when a time required for the cache process is shorter than or equal to a reference time, and selects virtual machine switching when the time required for the cache process is longer than the reference time.

2. The information processing device of claim 1 , wherein the nonvolatile semiconductor memory is used as a main memory.

3. The information processing device of claim 1 , further comprising:

first and second guest operating systems operating on each of the first and second virtual machines; and

an allocation determination section which determines an allocation area of data in at least one of the nonvolatile semiconductor memory and the semiconductor memory when writing the data, wherein

the first and second guest operating systems generate access frequency information on the data, the data being processed in the process executed on the operating system, and

the allocation determination section determines the allocation area of the data based on the access frequency information.

4. The information processing device of claim 3 , wherein

the allocation determination section determines the allocation area based on the access frequency information and each degree of wear of memory area in the nonvolatile semiconductor memory.

5. The information processing device of claim 1 , further comprising control software which is executed by a processor, the control software controlling the nonvolatile semiconductor memory to use as an auxiliary memory, and determining an allocation area of each data based on a file allocation table associated with the nonvolatile semiconductor memory or access frequency information of each data.

6. The information processing device of claim 1 , wherein

the virtual machine switching section comprises a management table managing an execution status of each of the first and second virtual machines, a time for enable, and a priority of execution, and switches the virtual machine in execution based on the management table.

7. The information processing device of claim 1 , wherein

the nonvolatile semiconductor memory includes a NAND flash memory of Single Level Cells and a NAND flash memory of Multi Level Cells.

8. The information processing device of claim 1 , wherein

the semiconductor memory is a volatile semiconductor memory.

9. An information processing device comprising:

an operating system which accesses a hardware resource including a nonvolatile semiconductor memory and a semiconductor memory used as a cache memory of the nonvolatile semiconductor memory;

first and second virtual machines operating on the operating system;

a cache-miss detection section which detects cache miss to the semiconductor memory in a process executed by the first virtual machine;

a cache control section which executes a cache process when the cache-miss detection section detects the cache miss in the process; and

a virtual machine switching section which, when the cache-miss detection section detects the cache miss in the process executed by the first virtual machine, switches a virtual machine in execution from the first virtual machine to the second virtual machine while the cache control section executes the cache process,

wherein the operating system selects thread switching when a time required for the cache process is shorter than or equal to a reference time, and selects virtual machine switching when the time required for the cache process is longer than the reference time.

10. An information processing method comprising:

operating first and second virtual machines on an operating system which accesses a hardware resource including a nonvolatile semiconductor memory and a semiconductor memory used as a cache memory of the nonvolatile semiconductor memory, by a processor;

detecting, by at least one of the processor and a memory management device, cache miss to the semiconductor memory in a process executed by the first virtual machine and, when the cache miss is detected, executing a cache process; and

switching a virtual machine in execution from the first virtual machine to the second virtual machine while the cache process is executed, by the at least one of the processor and the memory management device,

wherein the operating system selects process switching when a time required for the cache process is shorter than or equal to a reference time, and selects virtual machine switching when the time required for the cache process is longer than the reference time.

11. The information processing method of claim 10 , wherein the nonvolatile semiconductor memory is used as a main memory.

12. The information processing method of claim 11 , further comprising:

determining an allocation area of data in at least one of the nonvolatile semiconductor memory and the semiconductor memory, by the at least one of the processor and the memory management device, wherein

each of the first and second virtual machines operate first and second guest operating systems,

the first and second guest operating systems generate access frequency information on the data, the data being processed in the process executed on the operating system, and

the determining the allocation area determines the allocation area of the data based on the access frequency information.

13. The information processing method of claim 11 , further comprising:

executing, by a processor, control software determining an allocation area of each data based on a file allocation table associated with the nonvolatile semiconductor memory or access frequency information of each data, the control software controlling the nonvolatile semiconductor memory to use as an auxiliary memory.

14. The information processing method of claim 11 , wherein

the switching refers a management table managing an execution status of each of the first and second virtual machines, a time for enable, and a priority of execution, and switches the virtual machine in execution based on the management table.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 24, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043709/0035 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 13, 2011
From: KUNIMATSU, ATSUSHI; UEMURA, GOH; OWA, TSUTOMU
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 026432/0805 →
Priority Claims (1)
JP 2010-172048 · Jul 30, 2010 · national
Continuity (1)
Related Publication 20120030405A1 · Feb 2, 2012