IP Library Granted Patent US 9,142,547
Granted Patent B2
US 9,142,547 · App. 13/077,554 · Granted Sep 22, 2015

Methods of manufacturing resistors and structures thereof

Inventors: Knut Stahrenberg (Wappingers Falls, NY); Jin-Ping Han (Fishkill, NY)
Assignee: Infineon Technologies AG
H01L27/0629H01L28/20H01L21/823814
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Quick Facts
Patent No.
US 9,142,547
App. No.
13/077,554
Granted
Sep 22, 2015
Kind
B2
Abstract

A semiconductor device includes a semiconductor body of a first semiconductive material. A transistor is disposed in the semiconductor body. The transistor includes source and drain regions of a second semiconductive material embedded in the semiconductor body. A resistor overlies a top surface of the semiconductor body and is laterally spaced from the transistor. The resistor is formed from the second semiconductive material.

Claims (43)

1. A semiconductor device, comprising:

a semiconductor body of a first semiconductive material;

a transistor disposed in the semiconductor body, the transistor including a semiconductive gate region comprising the first semiconductive material and source and drain regions of a second semiconductive material, wherein the first semiconductive material and the second semiconductive material are different types of material, wherein the source and drain regions are embedded in the semiconductor body;

a semiconductive resistor overlying a top surface of the semiconductor body and laterally spaced from the transistor, the resistor comprising the second semiconductive material, the resistor and the gate region being a different type of semiconductor material, and the resistor and the source and drain regions being a same type of semiconductor material;

a gate dielectric layer overlying the top surface of the semiconductor body, wherein the resistor overlies the gate dielectric layer;

a first silicide region embedded at a first end of the semiconductive resistor;

a second silicide region embedded at a second end of the semiconductive resistor; and

an insulator layer contacting and covering a top surface of the semiconductive resistor, wherein a structure comprising the resistor is embedded in the insulator layer.

2. The device according to claim 1 , wherein the second semiconductive material of the resistor comprises a crystalline material.

3. The device according to claim 1 , wherein the second semiconductive material comprises SiGe.

4. The device according to claim 1 , wherein the second semiconductive material comprises Ge.

5. The device according to claim 1 , wherein the second semiconductive material comprises InP.

6. The device according to claim 1 , wherein the first semiconductive material comprises elemental silicon and the second semiconductive material comprises a compound semiconductor material.

7. The device according to claim 6 , wherein the second semiconductive material comprises SiGe.

8. The device according to claim 6 , wherein the second semiconductive material comprises InP.

9. The device according to claim 1 , wherein the first semiconductive material comprises elemental silicon and the second semiconductive material comprises an elemental semiconductive material other than silicon.

10. The device according to claim 9 , wherein the second semiconductive material comprises Ge.

11. The device according to claim 1 , wherein the transistor and resistor are implemented in a radio frequency (RF) circuit, an analog circuit, or a mixed signal circuit.

12. A semiconductor device, comprising:

a transistor disposed in a first region of a semiconductor body that comprises a first semiconductive material, the transistor including source and drain regions comprising a second semiconductive material that is a different type of material than the first semiconductive material, the transistor further including a gate dielectric material disposed over the semiconductor body and a gate comprising a metal layer disposed over the gate dielectric material and a semiconductor layer comprising the first semiconductive material disposed over the metal layer; and

a semiconductive resistor disposed above a second region of the semiconductor body, the second region being laterally spaced from the first region, the resistor comprising the second semiconductive material disposed over the gate dielectric material, the resistor and the first semiconductive material of the gate being a different type of semiconductor material, and the resistor and the source and drain regions being a same type of semiconductor material;

a first silicide region embedded at a first end of the semiconductive resistor;

a second silicide region embedded at a second end of the semiconductive resistor;

an insulator layer contacting and covering a top surface of the semiconductive resistor; and

a first elongated contact and a second elongated contact disposed in the insulator layer, the first and the second elongated contacts coupled to the resistor through the first and the second silicide regions.

13. The device according to claim 12 , wherein the source and drain regions are embedded in the semiconductor body and wherein the resistor overlies a top surface of the semiconductor body.

14. The device according to claim 12 , wherein the second semiconductive material of the resistor comprises a crystalline material.

15. The device according to claim 12 , wherein the first semiconductive material comprises elemental silicon and the second semiconductive material comprises a compound semiconductor material.

16. The device according to claim 15 , wherein the second semiconductive material comprises InP.

17. The device according to claim 15 , wherein the second semiconductive material comprises SiGe.

18. The device according to claim 12 , wherein the first semiconductive material comprises elemental silicon and the second semiconductive material comprises an elemental semiconductive material other than silicon.

19. The device according to claim 18 , wherein the second semiconductive material comprises Ge.

20. A method of fabricating a semiconductor device, the method comprising:

forming a transistor in a first region of a semiconductor body comprising a first semiconductive material, the transistor including source and drain regions comprising a second semiconductive material that is a different type of material than the first semiconductive material, the transistor including a gate dielectric material disposed over the semiconductor body and a gate comprising a metal layer disposed over the gate dielectric material and a semiconductor layer comprising the first semiconductive material disposed over the metal layer; and

forming a semiconductive resistor over a second region of the semiconductor body, the second region being laterally spaced from the first region, the resistor comprising the second semiconductive material disposed over the gate dielectric material, the resistor and the semiconductor layer being a different type of semiconductor material, and the resistor and the source and drain regions being a same type of semiconductor material;

embedding a first silicide region at a first end of the semiconductive resistor;

embedding a second silicide region embedded at a second end of the semiconductive resistor;

forming an insulator layer contacting and covering a top surface of the semiconductive resistor; and

forming a first elongated contact and a second elongated contact in the insulator layer, the first and the second elongated contacts coupled to the resistor through the first and the second silicide regions.

21. The method according to claim 20 , wherein the second semiconductive material of the resistor comprises a crystalline material.

22. The method according to claim 20 , wherein the second semiconductive material comprises SiGe, Ge, or InP.

23. The method according to claim 20 , wherein the first semiconductive material comprises elemental silicon and the second semiconductive material comprises a compound semiconductor material or an elemental semiconductive material other than silicon.

24. The method according to claim 20 , wherein the resistor is implemented in a radio frequency (RF) circuit, an analog circuit, or a mixed signal circuit.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 5, 2023
From: INFINEON TECHNOLOGIES AMERICAS CORP.
To: INFINEON TECHNOLOGIES AG
Reel/Frame 065758/0345 →
MERGER AND CHANGE OF NAME Recorded Sep 11, 2023
From: INFINEON TECHNOLOGIES NORTH AMERICA CORP.; INTERNATIONAL RECTIFIER CORPORATION
To: INFINEON TECHNOLOGIES AMERICAS CORP.
Reel/Frame 064854/0833 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 11, 2023
From: STAHRENBERG, KNUT; HAN, JIN-PING
To: INFINEON TECHNOLOGIES NORTH AMERICA CORP.
Reel/Frame 064854/0866 →
Continuity (2)
Division 12478905 · Jun 5, 2009
Related Publication 20110175174A1 · Jul 21, 2011