IP Library › Granted Patent US 8,431,449
Granted Patent B2
US 8,431,449 · App. 13/078,021 · Granted Apr 30, 2013

Manufacturing method of semiconductor device

Inventors: Hideomi Suzawa (Atsugi, JP); Shinya Sasagawa (Chigasaki, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
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Quick Facts
Patent No.
US 8,431,449
App. No.
13/078,021
Granted
Apr 30, 2013
Kind
B2
Abstract

An embodiment is a manufacturing method of a semiconductor device including the steps of forming a first insulating film; forming a first mask over the first insulating film; performing a slimming process on the first mask to form a second mask; performing an etching process on the first insulating film using the second mask to form a second insulating film; forming a first conductive film covering the second insulating film; performing a polishing process on the first conductive film and the second insulating film to form a third insulating film, a source electrode, and a drain electrode having equal thicknesses; forming an oxide semiconductor film over the third insulating film, the source electrode, and the drain electrode; forming a gate insulating film over the oxide semiconductor film; and forming a gate electrode in a region which is over the gate insulating film and overlaps with the third insulating film.

Claims (56)

1. A manufacturing method of a semiconductor device comprising the steps of:

forming a first insulating film over a substrate;

forming a first mask over the first insulating film;

performing a slimming process on the first mask, so that a second mask is formed;

performing an etching process on the first insulating film by using the second mask, so that a second insulating film is formed;

forming a first conductive film over the second insulating film and the substrate;

performing a polishing process on the first conductive film and the second insulating film, so that a third insulating film, a source electrode, and a drain electrode are formed;

forming an oxide semiconductor film over the third insulating film, the source electrode, and the drain electrode;

forming a gate insulating film over the oxide semiconductor film; and

forming a gate electrode in a region which is over the gate insulating film and overlaps with the third insulating film.

2. The manufacturing method of a semiconductor device according to claim 1 , wherein the polishing process is performed so that the third insulating film, the source electrode, and the drain electrode have substantially equal thicknesses.

3. The manufacturing method of a semiconductor device according to claim 1 , wherein a difference in height between a part of a surface of the third insulating film and a surface of the source electrode or a difference in height between a part of a surface of the third insulating film and a surface of the drain electrode is less than 5 nm.

4. The manufacturing method of a semiconductor device according to claim 1 , wherein the third insulating film has a thickness substantially equal to a thickness of the second insulating film.

5. The manufacturing method of a semiconductor device according to claim 1 , wherein the first insulating film is formed on a flat surface having a root-mean-square roughness of less than or equal to 1 nm.

6. The manufacturing method of a semiconductor device according to claim 1 , wherein the slimming process is performed using an ashing process using an oxygen radical.

7. The manufacturing method of a semiconductor device according to claim 1 , wherein the polishing process is performed using chemical mechanical polishing.

8. The manufacturing method of a semiconductor device according to claim 1 , wherein the first insulating film is formed by sputtering.

9. A manufacturing method of a semiconductor device comprising the steps of:

forming a first transistor including a channel formation region, a first gate electrode over the channel formation region with a first gate insulating film located between the channel formation region and the first gate electrode, and a first source electrode and a first drain electrode which are electrically connected to the channel formation region;

forming an interlayer insulating film over the first transistor;

forming a first insulating film over the interlayer insulating film;

forming a first mask over the first insulating film;

performing a slimming process on the first mask, so that a second mask is formed;

performing an etching process on the first insulating film by using the second mask, so that a second insulating film is formed;

forming a first conductive film over the second insulating film and the interlayer insulating film;

performing a polishing process on the first conductive film and the second insulating film, so that a third insulating film, a second source electrode, and a second drain electrode are formed;

forming an oxide semiconductor film over the third insulating film, the second source electrode, and the second drain electrode;

forming a second gate insulating film over the oxide semiconductor film; and

forming a second gate electrode in a region which is over the second gate insulating film and overlaps with the third insulating film.

10. The manufacturing method of a semiconductor device according to claim 9 , wherein the polishing process is performed so that the third insulating film, the second source electrode, and the second drain electrode have substantially equal thicknesses.

11. The manufacturing method of a semiconductor device according to claim 9 , wherein a difference in height between a part of a surface of the third insulating film and a surface of the second source electrode or a difference in height between a part of a surface of the third insulating film and a surface of the second drain electrode is less than 5 nm.

12. The manufacturing method of a semiconductor device according to claim 9 , wherein the third insulating film has a thickness substantially equal to a thickness of the second insulating film.

13. The manufacturing method of a semiconductor device according to claim 9 , wherein the interlayer insulating film has a flat surface having a root-mean-square roughness of less than or equal to 1 nm.

14. The manufacturing method of a semiconductor device according to claim 9 , wherein the slimming process is performed using an ashing process using an oxygen radical.

15. The manufacturing method of a semiconductor device according to claim 9 , wherein the polishing process is performed using chemical mechanical polishing.

16. The manufacturing method of a semiconductor device according to claim 9 , wherein the first insulating film is formed by sputtering.

17. A manufacturing method of a semiconductor device comprising the steps of:

forming a first gate electrode of a first transistor;

forming a first insulating film over the first gate electrode;

performing a first polishing process on the first insulating film;

forming a second insulating film over the first insulating film and the first gate electrode

forming a first mask over the second insulating film;

performing a slimming process on the first mask, so that a second mask is formed;

performing an etching process on the second insulating film by using the second mask, so that a third insulating film is formed;

forming a first conductive film over the third insulating film and the first insulating film;

performing a second polishing process on the first conductive film and the third insulating film, so that an electrode electrically connected to the first gate electrode and a fourth insulating film are formed;

forming an oxide semiconductor film over and in contact with the electrode and the fourth insulating film;

forming a second gate insulating film over the oxide semiconductor film; and

forming a second gate electrode in a region which is over the second gate insulating film and overlaps with the fourth insulating film.

18. The manufacturing method of a semiconductor device according to claim 17 , wherein the second polishing process is performed so that the fourth insulating film and the electrode have substantially equal thicknesses.

19. The manufacturing method of a semiconductor device according to claim 17 , wherein a difference in height between a part of a surface of the fourth insulating film and a surface of the electrode is less than 5 nm.

20. The manufacturing method of a semiconductor device according to claim 17 , wherein the fourth insulating film has a thickness substantially equal to a thickness of the third insulating film.

21. The manufacturing method of a semiconductor device according to claim 17 , wherein the second insulating film has a flat surface having a root-mean-square roughness of less than or equal to 1 nm.

22. The manufacturing method of a semiconductor device according to claim 17 , wherein the slimming process is performed using an ashing process using an oxygen radical.

23. The manufacturing method of a semiconductor device according to claim 17 , wherein the second polishing process is performed using chemical mechanical polishing.

24. The manufacturing method of a semiconductor device according to claim 17 , wherein the second insulating film is formed by sputtering.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 1, 2011
From: SUZAWA, HIDEOMI; SASAGAWA, SHINYA
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 026059/0145 →
Priority Claims (1)
JP 2010-090283 · Apr 9, 2010 · national
Continuity (1)
Related Publication 20110250724A1 · Oct 13, 2011