IP Library Granted Patent US 8,225,157
Granted Patent B2
US 8,225,157 · App. 13/078,621 · Granted Jul 17, 2012

Shadow protocol circuit having full and reduced pin select outputs

Assignee: Texas Instruments Incorporated
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Quick Facts
Patent No.
US 8,225,157
App. No.
13/078,621
Granted
Jul 17, 2012
Kind
B2
Abstract

The disclosure describes a process and apparatus for accessing devices on a substrate. The substrate may include only full pin JTAG devices ( 504 ), only reduced pin JTAG devices ( 506 ), or a mixture of both full pin and reduced pin JTAG devices. The access is accomplished using a single interface ( 502 ) between the substrate ( 408 ) and a JTAG controller ( 404 ). The access interface may be a wired interface or a wireless interface and may be used for JTAG based device testing, debugging, programming, or other type of JTAG based operation.

Claims (13)

1. An addressable test interface comprising:

A. substrate;

B. a test data input lead having an input and an output on the substrate;

C. a test clock lead having an input and an output on the substrate;

D. a test mode select lead having an input on the substrate;

E. a mode gate on the substrate, the mode gate having one input connected to the test mode select lead, another input, and an output connected to a gated test mode select lead on the substrate;

F. a test data output lead having an input on the substrate;

G. a tri-state gate on the substrate, the tri-state gate having an input connected to the test data output lead, an enable input, and an output connected to a gated test data output lead on the substrate; and

H. a shadow protocol circuit on the substrate, the circuit having inputs connected to the test data lead, the test clock lead, and the test mode select lead, and having a first interface select output, and a second interface select output.

2. The addressable test interface of claim 1 in which the substrate is an IC.

3. The addressable test interface of claim 1 in which the substrate is a board.

4. The addressable test interface of claim 1 in which the substrate is a system.

5. The addressable test interface of claim 1 in which the shadow protocol circuit includes an enable output connected to the other input of the mode gate and an enable output connected to the enable input of the tri-state gate.

Continuity (4)
Division 12883629 · Sep 16, 2010
Division 11874594 · Oct 18, 2007
Provisional Application 60829979 · Oct 18, 2006
Related Publication 20110185242A1 · Jul 28, 2011