IP Library › Granted Patent US 8,738,313
Granted Patent B2
US 8,738,313 · App. 13/079,461 · Granted May 27, 2014

Measurement apparatus

Inventor: Koji Ota (Musashino, JP)
Assignee: Yokogawa Electric Corporation
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Quick Facts
Patent No.
US 8,738,313
App. No.
13/079,461
Granted
May 27, 2014
Kind
B2
Abstract

An apparatus is realized which is capable of shortening the updating period of the measurement of a specific channel and lengthening the updating period of the measurement for another channel, thereby making the measurements for all the channels possible. The measurement apparatus includes a multiplexer that sequentially switches between analog input signals of a plurality of channels and internal calibration signals; an analog-to-digital converter that converts the signals from an analog to digital form; and a digital processor to which the signals are input, wherein the digital processor includes a sequence operation unit for sequentially switching between a combination of a channel for which a high-speed update is necessary and another channel, and the internal calibration signal among the input signals of the plurality of channels and supplying, to the multiplexer, an operation signal that is input to the AD converter.

Claims (9)

1. A measurement apparatus comprising:

a plurality of channels for inputting signals;

a multiplexer that sequentially switches between a first signal and a second signal of said signals;

sequence-operation means for controlling said switching performed by said multiplexer;

an AD converter that performs AD conversion of said first signal or second signal which is selected by said multiplexer; and

a digital processor that performs measurement of at least one of the channels based on an output from said AD converter,

wherein said first signal is a signal of an input channel for which a high-speed update is necessary,

wherein said second signal is a signal of an input channel, for which a high-speed update is unnecessary, or an internal calibration signal which is at least one of a zero adjustment signal, a span adjustment signal, and an internal terminal temperature signal, and

wherein said digital processor performs measurement of the channels for at least two pairs of said first and second signals, one pair including said first signal and said second signal that is the signal of the input channel for which the high-speed update is unnecessary and another pair including said first signal and said second signal that is the internal calibration signal.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 28, 2011
From: OTA, KOJI
To: YOKOGAWA ELECTRIC CORPORATION
Reel/Frame 026195/0252 →
Priority Claims (1)
JP 2010-086694 · May 4, 2010 · national
Continuity (1)
Related Publication 20110276294A1 · Nov 10, 2011