Technique to generate divide by two and 25% duty cycle

1. A frequency divider, comprising:

an input configured to receive a clock signal, each cycle of the clock signal including a first phase and a second phase;

a plurality of latches; and

a plurality of three-state circuits wherein a first of the plurality of three-state circuits is configured to drive a first twenty-five percent duty cycle signal from within the first three-state circuit high during a first phase of a first of two clock cycles.

2. A frequency divider according to claim 1 , wherein:

a second of the plurality of three-state circuits is configured to drive a second twenty-five percent duty cycle signal from within the second three-state circuit high during a second phase of the first of two clock cycles;

a third of the plurality of three-state circuits is configured to drive a third twenty-five percent duty cycle signal from within the third three-state circuit high during a first phase of a second of two clock cycles; and

a fourth of the plurality of three-state circuits is configured to drive a fourth twenty-five percent duty cycle signal from within the fourth three-state circuit high during a second phase of the second of two clock cycles.

3. A frequency divider according to claim 2 , wherein:

a loop input of the fourth three-state circuit is coupled to a loop output of the first three-state circuit and a first terminal of a first latch of the plurality of latches;

a loop input of the third three-state circuit is coupled to a loop output of the fourth three-state circuit and a first terminal of a second latch of the plurality of latches;

a loop input of the second three-state circuit is coupled to a loop output of the third three-state circuit and a second terminal of the first latch; and

a loop input of the first three-state circuit is coupled to a loop output of the second three-state circuit and a second terminal of the second latch.

4. A frequency divider according to claim 3 , wherein:

the first latch comprises a first inverter cross-coupled with a second inverter; and

the second latch comprises a first inverter cross-coupled with a second inverter.

5. A frequency divider according to claim 4 , wherein:

the first latch is configured to be subservient when the loop input of the second three-state circuit is driven by the loop output of the third three-state circuit and the loop input of the fourth three-state circuit is driven by the loop output of the first three-state circuit and to latch the loop input of the second three-state circuit and the loop input of the fourth three state circuit when the loop output of the third three-state circuit and the loop output of the first three-state circuit are in a high-impedance state; and

the second latch is configured to be subservient when the loop input of the first three-state circuit is driven by the loop output of the second three-state circuit and the loop input of the third three-state circuit is driven by the loop output of the fourth three-state circuit and to latch the loop input of the first three-state circuit and the loop input of the third three-state circuit when the loop output of the second three-state circuit and the loop output of the fourth three-state circuit are in a high-impedance state.

6. A frequency divider according to claim 1 , wherein the first three-state circuit comprises:

a p-type metal-oxide semiconductor transistor (PMOS) having a gate coupled to a loop input of the first three-state circuit and a source coupled to a high potential power supply;

an n-type metal-oxide semiconductor transistor (NMOS) having a gate coupled to the loop input of the first three-state circuit and a source coupled to a low potential power supply;

a first pass gate having a first conducting terminal coupled to a drain of the PMOS and a second conducting terminal coupled to a loop output of the first three-state circuit; and

a second pass gate having a first conducting terminal coupled to a drain of the NMOS and a second conducting terminal coupled the loop output of the first three-state circuit.

7. A frequency divider according to claim 6 , wherein the drain of the PMOS is not directly coupled to the drain of the NMOS.

8. A frequency divider according to claim 7 , wherein:

the first pass gate comprises a PMOS; and

the second pass gate comprises an NMOS.

9. A frequency divider according to claim 7 , wherein:

the first pass gate comprises an NMOS; and

the second pass gate comprises an NMOS.

10. A frequency divider according to claim 7 , wherein:

the first pass gate comprises a PMOS; and

the second pass gate comprises a PMOS.

11. A receiver, comprising:

a downconverter configured to downconvert a radio-frequency (RF) signal;

a local oscillator circuit configured to drive at least one mixer within the downconverter, the local oscillator circuit comprising:

an oscillator configured to generate a clock signal, each cycle of the clock signal having a first phase and a second phase; and

a frequency divider comprising:

an input configured to receive the clock signal;

a plurality of latches; and

a plurality of three-state circuits wherein a first of the plurality of three-state circuits is configured to drive a first twenty-five percent duty cycle signal from within the first three-state circuit high during a first phase of a first of two clock cycles.

12. A receiver according to claim 11 , the frequency divider further comprising:

a second of the plurality of three-state circuits is configured to drive a second twenty-five percent duty cycle signal from within the second three-state circuit high during a second phase of the first of two clock cycles;

a third of the plurality of three-state circuits is configured to drive a third twenty-five percent duty cycle signal from within the third three-state circuit high during a first phase of a second of two clock cycles; and

a fourth of the plurality of three-state circuits is configured to drive a fourth twenty-five percent duty cycle signal from within the fourth three-state circuit high during a second phase of the second of two clock cycles.

13. A receiver according to claim 12 , wherein:

a loop input of the fourth three-state circuit is coupled to a loop output of the first three-state circuit and a first terminal of a first latch of the plurality of latches;

a loop input of the third three-state circuit is coupled to a loop output of the fourth three-state circuit and a first terminal of a second latch of the plurality of latches;

a loop input of the second three-state circuit is coupled to a loop output of the third three-state circuit and a second terminal of the first latch; and

a loop input of the first three-state circuit is coupled to a loop output of the second three-state circuit and a second terminal of the second latch.

14. A receiver according to claim 13 , wherein:

the first latch comprises a first inverter cross-coupled with a second inverter, the first latch configured to be subservient when the loop input of the second three-state circuit is driven by the loop output of the third three-state circuit and the loop input of the fourth three-state circuit is driven by the loop output of the first three-state circuit and to latch the loop input of the second three-state circuit and the loop input of the fourth three state circuit when the loop output of the third three-state circuit and the loop output of the first three-state circuit are in a high-impedance state; and

the second latch comprises a first inverter cross-coupled with a second inverter, the second latch configured to be subservient when the loop input of the first three-state circuit is driven by the loop output of the second three-state circuit and the loop input of the third three-state circuit is driven by the loop output of the fourth three-state circuit and to latch the loop input of the first three-state circuit and the loop input of the third three-state circuit when the loop output of the second three-state circuit and the loop output of the fourth three-state circuit are in a high-impedance state.

15. A receiver according to claim 11 , wherein the first three-state circuit comprises:

a p-type metal-oxide semiconductor transistor (PMOS) having a gate coupled to a loop input of the first three-state circuit and a source coupled to a high potential power supply;

an n-type metal-oxide semiconductor transistor (NMOS) having a gate coupled to the loop input of the first three-state circuit, and a source coupled to a low potential power supply;

a first pass gate having a first conducting terminal coupled to a drain of the PMOS and a second conducting terminal coupled to a loop output of the first three-state circuit; and

a second pass gate having a first conducting terminal coupled to a drain of the NMOS and a second conducting terminal coupled the loop output of the first three-state circuit.

16. A receiver according to claim 15 , wherein the drain of the PMOS is not directly coupled to the drain of the NMOS.

17. A receiver according to claim 11 , wherein the downconverter is configured to perform quadrature mixing.

18. A method for generating at least one frequency-divided twenty-five percent duty cycle signal comprising:

receiving a clock signal, each cycle of the clock signal having a first phase and a second phase; and

driving a first twenty-five percent duty cycle output from within a first three-state circuit high during a first phase of a first of two clock cycles.

19. A method according to claim 18 , further comprising:

driving a second twenty-five percent duty cycle output from within a second three-state circuit high during a second phase of the first of two clock cycles;

driving a third twenty-five percent duty cycle output from within a third three-state circuit high during a first phase of a second of two clock cycles; and

driving a fourth twenty-five percent duty cycle output from within a fourth three-state circuit high during a second phase of the second of two clock cycles.

20. A method according to claim 18 , further comprising generating a frequency-divided signal having a low state during the first clock cycle of two clock cycles and a high state during the second clock cycle of two clock cycles.

21. A method according to claim 20 , further comprising inverting the low state of the frequency-divided signal to create an inverted frequency-divided signal at a first node within the first three-state circuit during the first of two clock cycles.

22. A method according to claim 21 , further comprising passing the inverted frequency-divided signal at the first node within the first three-state circuit to a second node within the first three-state circuit during the first phase of the first out of two cycles.