IP Library Granted Patent US 8,413,085
Granted Patent B2
US 8,413,085 · App. 13/083,534 · Granted Apr 2, 2013

Digital netlist partitioning system for faster circuit reverse-engineering

Inventor: Michael Green (Ottawa, CA)
Assignee: Chipworks Inc.
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Quick Facts
Patent No.
US 8,413,085
App. No.
13/083,534
Granted
Apr 2, 2013
Kind
B2
Abstract

Methods and systems are provided to reduce the complexity of sequential digital circuitry including cells of unknown function by grouping and defining like instance of combinational circuitry cells. The system groups together cells that feed into the same combination of one or more state cells. The groups of cells are then replaced by clouds which are defined in the netlist for the sequential digital circuitry to produce a simpler representation of the circuitry for analysis purposes and to aid in determining the function of those cells for which the function is unknown.

Claims (46)

1. A method of reducing complexity of a digital circuit comprising:

providing circuitry for analysis comprising a plurality of cells, wherein at least some of the plurality of cells have an unknown function;

categorizing each of the plurality of cells as either a combinational cell or a state cell, wherein the plurality of cells comprise a plurality of combinational cells and a plurality of state cells;

identifying by a computer a first combinational cell group among the plurality of combinational cells that each affect a same portion of the plurality of state cells; and

replacing the first combinational cell group with a first cloud.

2. The method of claim 1 , further comprising:

identifying a plurality of buffers within said plurality of cells; and

replacing said plurality of buffers with a single buffer cell.

3. The method of claim 2 , wherein the identifying of said plurality of buffers is based on identifying cells having only a single input and a single output.

4. The method of claim 1 , wherein the providing of the circuitry comprises:

selecting the circuitry from a netlist that characterizes said digital circuit.

5. The method of claim 4 , wherein the netlist is an original netlist, the method further comprising:

including said first cloud in a reduced-size netlist smaller than said original netlist that characterizes said digital circuit;

wherein the first cloud replaces the first combinational cell group in said reduced size netlist.

6. The method of claim 1 , further comprising:

including said first cloud in a reduced size netlist that characterizes said digital circuit; and

using said reduced size netlist to analyze circuitry functions of said digital circuit for determining a function of cells having an unknown function.

7. The method of claim 1 , wherein the plurality of state cells includes a first state cell and a second state cell; and wherein the first combinational cell group is defined to consist of cells that affect only inputs of both the first state cell and the second state cell.

8. The method of claim 7 , further comprising:

defining a second combinational cell group to consist of cells that affect only inputs of the first state cell.

9. The method of claim 8 , further comprising:

replacing the second combinational cell group with a second cloud; and

including said second cloud in a reduced-size netlist that characterizes said digital circuit.

10. A computer program product comprising computer instructions stored on a nontransitory computer readable medium for reducing complexity of a digital circuit, said computer instructions upon being executed on a computer are configured to perform activities comprising:

providing circuitry for analysis comprising a plurality of cells, wherein at least some of the plurality of cells have an unknown function;

categorizing each of the plurality of cells as either a combinational cell or a state cell, wherein the plurality of cells comprise a plurality of combinational cells and a plurality of state cells;

identifying a first combinational cell group among the plurality of combinational cells that each affect a same portion of the plurality of state cells; and

replacing the first combinational cell group with a first cloud.

11. The computer program product of claim 10 , further comprising:

identifying a plurality of buffers within said plurality of cells; and

replacing said plurality of buffers with a single buffer cell.

12. The computer program product of claim 11 , wherein the identifying of said plurality buffers is based on identifying cells having only a single input and a single output.

13. The computer program product of claim 10 , wherein the providing of the circuitry comprises:

selecting the circuitry from a netlist that characterizes said digital circuit.

14. The computer program product of claim 13 , wherein the netlist is an original netlist, the method further comprising:

including said first cloud in a reduced-size netlist smaller than said original netlist that characterizes said digital circuit;

wherein the first cloud replaces the first combinational cell group in said reduced size netlist.

15. The computer program product of claim 10 , further comprising:

including said first cloud in a reduced-size netlist that characterizes said digital circuit; and

using said reduced size netlist to analyze circuitry functions of said digital circuit for determining a function of cells having an unknown function.

16. The computer program product of claim 10 , wherein the plurality of state cells includes a first state cell and a second state cell; and wherein the first combinational cell group is defined to consist of cells that affect only inputs of both the first state cell and the second state cell.

17. The computer program product of claim 10 , further comprising:

defining a second combinational cell group to consist of cells that affect only inputs of the first state cell.

18. The computer program product of claim 17 , further comprising:

replacing the second combinational cell group with a second cloud; and

including said second cloud in a reduced-size netlist that characterizes said digital circuit.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2021
From: STELLUS CAPITAL INVESTMENT CORPORATION, AS ADMINISTRATIVE AGENT
To: TECHINSIGHTS INC.
Reel/Frame 058096/0558 →
SECURITY INTEREST Recorded Nov 10, 2021
From: TECHINSIGHTS INC.; VLSI RESEARCH INC.
To: CAPITAL ONE, NATIONAL ASSOCIATION
Reel/Frame 058096/0721 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 20, 2018
From: CHIPWORKS, INCORPORATED
To: TECHINSIGHTS INC.
Reel/Frame 046143/0649 →
NOTICE OF GRANT OF SECURITY INTEREST IN PATENTS Recorded Aug 16, 2017
From: TECHINSIGHTS INC.
To: STELLUS CAPITAL INVESTMENT CORPORATION, AS ADMINISTRATIVE AGENT
Reel/Frame 043571/0385 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 20, 2011
From: GREEN, MICHAEL
To: CHIPWORKS, INCORPORATED
Reel/Frame 026161/0695 →
Continuity (1)
Related Publication 20120260224A1 · Oct 11, 2012