IP Library Granted Patent US 8,758,537
Granted Patent B2
US 8,758,537 · App. 13/087,431 · Granted Jun 24, 2014

Method for producing a multiplicity of semiconductor wafers by processing a single crystal

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,758,537
App. No.
13/087,431
Granted
Jun 24, 2014
Kind
B2
Abstract

A method for producing a plurality of semiconductor wafers includes processing a single crystal. The single crystal is provided in a grown state and has a central longitudinal axis with an orientation that deviates from a sought orientation of a crystal lattice of the semiconductor wafers. A block is sliced from the single crystal along cutting planes perpendicular to a crystallographic axis corresponding to the sought orientation of the crystal lattice of the semiconductor wafers. A lateral surface of the block is ground around the crystallographic axis. A plurality of semiconductor wafers are then sliced from the ground block along cutting planes perpendicular to the crystallographic axis.

Claims (13)

1. A method for producing a plurality of semiconductor wafers by processing a single crystal, the method comprising:

providing a single crystal in an as-grown state, the single crystal having a central longitudinal axis with an orientation that deviates from a sought orientation of a crystal lattice of the semiconductor wafers;

slicing at least one block from the single crystal along cutting planes perpendicular to a crystallographic axis corresponding to the sought orientation of the crystal lattice of the semiconductor wafers;

grinding a lateral surface of the at least one block around the crystallographic axis so as to form at least one ground block with a central longitudinal axis substantially parallel to the crystallographic axis; and

slicing a plurality of semiconductor wafers from at least one ground block along cutting planes perpendicular to the crystallographic axis.

2. The method recited in claim 1 , further comprising determining a position of the crystallographic axis using surfaces that are visible on the single crystal and that have a known orientation as reference planes.

3. The method recited in claim 1 , wherein the slicing the at least one block from the single crystal includes using a band saw.

4. The method recited in claim 1 , further comprising marking the at least one block with a mark indicating a reference direction in a plane of the semiconductor wafers.

5. The method recited in claim 1 , wherein the at least one ground block includes a first block and a second block,

further comprising arranging the first block adjacent to the second block,

and wherein the slicing the plurality of semiconductor wafers includes using a multi wire saw to slice the semiconductor wafers from the first and second block.

6. The method recited in claim 5 , further comprising adhesively bonding the first block to the second block before slicing the plurality of semiconductor wafers.

7. The method recited in claim 1 , wherein the slicing at least one block from the single crystal is carried out with the single crystal in the as-grown state.

Assignments (3)
CORRECTIVE ASSIGNMENT TO CORRECT THE DATE OF THE CHANGE OF ADDRESS FROM 03/12/2020 TO 12/03/2020 PREVIOUSLY RECORDED AT REEL: 056719 FRAME: 0881. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jul 1, 2021
From: SILTRONIC AG
To: SILTRONIC AG
Reel/Frame 057561/0451 →
CHANGE OF ADDRESS Recorded Jun 30, 2021
From: SILTRONIC AG
To: SILTRONIC AG
Reel/Frame 056719/0881 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 15, 2011
From: OELKRUG, HANS; SCHUSTER, JOSEF
To: SILTRONIC AG
Reel/Frame 026133/0375 →