IP Library › Granted Patent US 8,234,436
Granted Patent B2
US 8,234,436 · App. 13/087,912 · Granted Jul 31, 2012

Computer system including peripheral bridge to communicate serial bits of peripheral component interconnect bus transaction and low voltage differential signal channel to convey the serial bits

Assignee: ACQIS LLC
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,234,436
App. No.
13/087,912
Granted
Jul 31, 2012
Kind
B2
Abstract

A computer system for multi-processing purposes. The computer system has a console comprising a first coupling site and a second coupling site. Each coupling site comprises a connector. The console is an enclosure that is capable of housing each coupling site. The system also has a plurality of computer modules, where each of the computer modules is coupled to a connector. Each of the computer modules has a processing unit, a main memory coupled to the processing unit, a graphics controller coupled to the processing unit, and a mass storage device coupled to the processing unit. Each of the computer modules is substantially similar in design to each other to provide independent processing of each of the computer modules in the computer system.

Claims (32)

1. A modular computer system comprising:

a modular computer comprising

a connector configured to couple to a console;

a first low voltage differential signal (LVDS) channel comprising at least two sets of unidirectional, multiple serial bit channels to convey data in opposite directions;

an integrated central processing unit and graphics controller configured as a single chip, the integrated central processing unit and graphics controller comprising an interface directly coupled to the first LVDS channel to communicate encoded address and data bits of Peripheral Component Interconnect (PCI) bus transaction in serial form over the first LVDS channel; and

a system memory directly coupled to the integrated central processing unit and graphics controller,

wherein the connector is configured to convey the encoded address and data bits of PCI bus transaction in serial form to the console upon coupling the connector to the console.

2. The modular computer system of claim 1 , further comprising a second LVDS channel coupled to the integrated central processing unit and graphics controller to convey digital video data.

3. The modular computer system of claim 1 , further comprising the console, and the console comprises an interface controller that is configured to couple to the connector for communication of the encoded address and data bits of PCI bus transaction in serial form.

4. The modular computer system of claim 2 , wherein the connector is coupled to the integrated central processing unit and graphics controller through the second LVDS channel, and the connector is configured to convey the digital video data to the console upon coupling the connector to the console.

5. The modular computer system of claim 4 , further comprising the console, the console comprises a LCD display, and the console is configured to receive the digital video data from the integrated central processing unit and graphics controller through the second LVDS channel and the connector.

6. The modular computer system of claim 3 , wherein the console comprises a mass storage device coupled to the interface controller.

7. A modular computer system comprising:

a modular computer comprising

a connector configured to couple to a console;

a first low voltage differential signal (LVDS) channel comprising at least two sets of unidirectional, multiple serial bit channels to convey data in opposite directions;

an integrated central processing unit and graphics controller configured as a single chip;

a peripheral bridge directly coupled to the integrated central processing unit and graphics controller without any intervening Peripheral Component Interconnect (PCI) bus, the peripheral bridge directly coupled to the first LVDS channel to communicate encoded address and data bits of PCI bus transaction in serial form over the first LVDS channel; and

a system memory directly coupled to the integrated central processing unit and graphics controller,

wherein the connector is configured to convey the encoded address and data bits of PCI bus transaction in serial form to the console upon coupling the connector to the console.

8. The modular computer system of claim 7 , further comprising a second LVDS channel coupled to the integrated central processing unit and graphics controller to convey digital video data.

9. The modular computer system of claim 7 , further comprising the console, and the console comprises an interface controller that is configured to couple to the connector for communication of the encoded address and data bits of PCI bus transaction in serial form.

10. The modular computer system of claim 8 , wherein the connector is coupled to the integrated central processing unit and graphics controller through the second LVDS channel, and the connector is configured to convey the digital video data to the console upon coupling the connector to the console.

11. The modular computer system of claim 10 , further comprising the console, the console comprises a LCD display, and the console is configured to receive the digital video data from the integrated central processing unit and graphics controller through the second LVDS channel and the connector.

12. The modular computer system of claim 9 , wherein the console comprises a mass storage device coupled to the interface controller.

13. A computer system comprising:

a first low voltage differential signal (LVDS) channel comprising at least two sets of unidirectional, multiple serial bit channels to convey data in opposite directions;

a central processing unit comprising a peripheral controller integrated with the central processing unit as a single chip, the peripheral controller directly coupled to the first LVDS channel to communicate encoded address and data bits of Peripheral Component Interconnect (PCI) bus transaction in serial form over the first LVDS channel;

a system memory directly coupled to the central processing unit; and

a mass storage device coupled to the central processing unit;

wherein the central processing unit comprises a graphics controller integrated in the single chip, and further comprising a second LVDS channel directly coupled to the graphics controller in the single chip to convey digital video data.

14. The computer system of claim 13 , further comprising an enclosure with a connector, and the connector is coupled to the first LVDS channel to convey the encoded address and data bits of PCI bus transaction in LVDS form.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 21, 2011
From: ACQIS TECHNOLOGY, INC.
To: ACQIS LLC
Reel/Frame 026628/0332 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 20, 2011
From: CHU, WILLIAM W.Y.
To: ACQIS TECHNOLOGY, INC.
Reel/Frame 026624/0338 →
Continuity (8)
Continuation 12504534 · Jul 16, 2009
Continuation 12077503 · Mar 18, 2008
Continuation 11166656 · Jun 24, 2005
Continuation 11097694 · Mar 31, 2005
Continuation 10772214 · Feb 3, 2004
Continuation 09569758 · May 12, 2000
Provisional Application 60134122 · May 14, 1999
Related Publication 20110208893A1 · Aug 25, 2011