Lateral power MOSFET
A lateral power MOSFET structure is disclosed. In some embodiments, a semiconductor device comprises substantially concentric source, channel, and drain regions; a metal layer at least in part comprising a drain plane disposed over the source, channel, and drain regions; and a metal layer at least in part comprising a source plane disposed over the source, channel, and drain regions.
1. A semiconductor device, comprising:
a source region completely surrounded by substantially concentric channel and drain regions and a central body contact encircled by the source region;
a first inner metal layer comprising a first drain plane disposed over the source, channel, and drain regions, wherein the first inner metal layer comprises a single plane that has one or more openings for connections;
a second inner metal layer comprising a second drain plane disposed over the first inner metal layer, wherein the second inner metal layer comprises a single plane that has one or more openings for connections; and
a top metal layer comprising a top source plane disposed over the inner metal layers, wherein the top source plane comprises a single plane that substantially comprises the top metal layer.
2. The semiconductor device of claim 1 , wherein each of the source, channel, and drain regions comprises a closed shape.
3. The semiconductor device of claim 1 , wherein each of the source, channel, and drain regions comprises a doughnut or a ring shape.
4. The semiconductor device of claim 1 , wherein each of the source, channel, and drain regions comprises a hexagon, octagon, square, rectangle, or circle.
5. The semiconductor device of claim 1 , further comprising a gate that controls the channel region, wherein the gate has a similar shape as and is substantially concentrically situated between the source and drain regions.
6. The semiconductor device of claim 1 , wherein the first inner metal layer and the second inner metal layer comprise source plates in the corresponding one or more openings.
7. The semiconductor device of claim 1 , wherein the source, channel, and drain regions are substantially identically shaped.
8. The semiconductor device of claim 1 , further comprising one or more additional inner metal layers comprising one or more additional drain planes, source planes, or both.
9. The semiconductor device of claim 1 , wherein the source region is connected to a body of the semiconductor device at an overlaying metal layer.
10. The semiconductor device of claim 1 , wherein the top metal layer has fewer interruptions and a lower resistance than any of the inner metal layers.
11. The semiconductor device of claim 1 , wherein the source and drain regions are connected to corresponding overlaying metal layers by one or more associated contacts.
12. The semiconductor device of claim 1 , wherein different metal layers have different thicknesses.
13. The semiconductor device of claim 1 , wherein the top metal layer is thicker than any of the inner metal layers.
14. The semiconductor device of claim 1 , wherein the source, channel, and drain regions comprise a single cell of an array of cells comprising the semiconductor device.
15. The semiconductor device of claim 14 , wherein at least a subset of cells comprising the array are connected in parallel.
16. The semiconductor device of claim 1 , wherein the source, channel, and drain regions are associated with a first MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and further comprising source, channel, and drain regions associated with a second MOSFET, wherein the first MOSFET and the second MOSFET are connected in a bi-directional back-to-back configuration.
17. The semiconductor device of claim 1 , wherein the semiconductor device is integrated on a same die with other circuitry.
18. The semiconductor device of claim 1 , wherein the semiconductor device comprises a lateral power MOSFET (Metal Oxide Semiconductor Field Effect Transistor).
19. A method for constructing a semiconductor device, comprising:
configuring a source region to be completely surrounded by substantially concentric channel and drain regions and wherein the source region encircles a central body contact;
disposing over the source, channel, and drain regions a first inner metal layer comprising a first drain plane, wherein the first inner metal layer comprises a single plane that has one or more openings for connections;
disposing over the first inner metal layer a second inner metal layer comprising a second drain plane, wherein the second inner metal layer comprises a single plane that has one or more openings for connections; and
disposing over the inner metal layers a top metal layer comprising a top source plane, wherein the top source plane comprises a single plane that substantially comprises the top metal layer.
20. The method of claim 19 , wherein each of the source, channel, and drain regions comprises a closed shape.
21. The method of claim 19 , wherein each of the source, channel, and drain regions comprises a doughnut or a ring shape.
22. The method of claim 19 , wherein each of the source, channel, and drain regions comprises a hexagon, octagon, square, rectangle, or circle.
23. The method of claim 19 , further comprising configuring a gate that controls the channel region, wherein the gate has a similar shape as and is substantially concentrically situated between the source and drain regions.
24. The method of claim 19 , wherein the first inner metal layer and the second inner metal layer comprise source plates in the corresponding one or more openings.
25. The method of claim 19 , wherein the source, channel, and drain regions are substantially identically shaped.
26. The method of claim 19 , further comprising disposing one or more additional inner metal layers comprising one or more additional drain planes, source planes, or both.
27. The method of claim 19 , wherein the source region is connected to a body of the semiconductor device at an overlaying metal layer.
28. The method of claim 19 , wherein the top metal layer has fewer interruptions and a lower resistance than any of the inner metal layers.
29. The method of claim 19 , wherein the source and drain regions are connected to corresponding overlaying metal layers by one or more associated contacts.
30. The method of claim 19 , wherein different metal layers have different thicknesses.
31. The method of claim 19 , wherein the top metal layer is thicker than any of the inner metal layers.
32. The method of claim 19 , wherein the source, channel, and drain regions comprise a single cell of an array of cells comprising the semiconductor device.
33. The method of claim 32 , wherein at least a subset of cells comprising the array are connected in parallel.
34. The method of claim 19 , wherein the source, channel, and drain regions are associated with a first MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and further comprising source, channel, and drain regions associated with a second MOSFET, wherein the first MOSFET and the second MOSFET are connected in a bi-directional back-to-back configuration.
35. The method of claim 19 , wherein the semiconductor device is integrated on a same die with other circuitry.
36. The method of claim 19 , wherein the semiconductor device comprises a lateral power MOSFET (Metal Oxide Semiconductor Field Effect Transistor).