IP Library Granted Patent US 8,416,024
Granted Patent B2
US 8,416,024 · App. 13/089,385 · Granted Apr 9, 2013

Impedance matching arrangement for amplifier having split shunt capacitor and amplifier including the same

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Quick Facts
Patent No.
US 8,416,024
App. No.
13/089,385
Granted
Apr 9, 2013
Kind
B2
Abstract

An amplifier having an operating frequency includes: an input port and an output port; three gain elements, each having an input terminal and an output terminal; an input matching network; and an output matching network. The input matching network includes: a first microstrip line which is connected to the input port and is an inductor at the operating frequency; a second microstrip line extending between the input terminals of the three gain elements; and a first split shunt capacitor connecting the first microstrip line to the second microstrip line. The output matching network includes: a third microstrip line which is connected to the output port and is an inductor at the operating frequency; a fourth microstrip line extending between the output terminals of the three gain elements; and a second split shunt capacitor connecting the third microstrip line to the fourth microstrip line.

Claims (60)

1. An amplifier, comprising:

an input port and an output port;

first, second, and third gain elements, each having an input terminal and an output terminal;

an input matching network connected between the input port and the input terminals of the first, second, and third gain elements; and

an output matching network connected between the input port and the output terminals of the first, second, and third gain elements,

wherein the input matching network comprises:

a first input capacitor having a first electrode and having a second electrode connected to a supply voltage,

a second input capacitor having a first electrode and having a second electrode connected to the supply voltage,

a first input inductor connected between the input port and the first electrodes of the first and second input capacitors;

a second input inductor connected between the first electrode of the first input capacitor and the input terminal of the first gain element,

a third input inductor connected between the first electrode of the first input capacitor and the input terminal of the second gain element,

a fourth input inductor connected between the first electrode of the second input capacitor and the input terminal of the second gain element, and

a fifth input inductor connected between the first electrode of the second input capacitor and the input terminal of the third gain element, and

wherein the output matching network comprises:

first output capacitor having a first electrode and having a second electrode connected to the supply voltage,

a second output capacitor having a first electrode and having a second electrode connected to the supply voltage,

a first output inductor connected between the output port and the first electrodes of the first and second output capacitors;

a second output inductor connected between the first electrode of the first output capacitor and the output terminal of the first gain element,

a third output inductor connected between the first electrode of the first output capacitor and the input terminal of the second gain element,

a fourth output inductor connected between the first electrode of the second output capacitor and the output terminal of the second gain element, and

a fifth output inductor connected between the first electrode of the second output capacitor and the output terminal of the third gain element.

2. The amplifier of claim 1 , further comprising:

a first tapered connector that connects the first input inductor and the first electrodes of the first and second input capacitors; and

a second tapered connector that connects the first output inductor and the first electrodes of the first and second output capacitors.

3. The amplifier of claim 1 , wherein the second electrodes of the first and second input capacitors comprises a common electrode having a through-hole disposed therein connecting the common electrode to the supply voltage.

4. The amplifier of claim 3 , wherein the supply voltage is ground.

5. The amplifier of claim 3 , wherein the first electrodes of the first and second input capacitors are disposed on opposite sides of the common electrode.

6. The amplifier of claim 5 , wherein the first electrodes of the first and second input capacitors and the common electrode are all disposed in a same surface of a semiconductor substrate

7. The amplifier of claim 1 , wherein the first input inductor comprises a microstrip

8. The amplifier of claim 1 , wherein the second, third, fourth and fifth input inductors all comprise a common microstrip line extending from the input terminal of the first gain element, past the input terminal of the second gain element, to the input terminal of the third gain element.

9. The amplifier of claim 1 , wherein the first, second, and third gain elements are all field effect transistors each having a third terminal connected to ground.

10. The amplifier of claim 1 , wherein the second electrodes of the first and second output capacitors comprises a common electrode having a through-hole disposed therein connecting the common electrode to the supply voltage.

11. The amplifier of claim 10 , wherein the supply voltage is ground.

12. The amplifier of claim 10 , wherein the first electrodes of the first and second output capacitors are disposed on opposite sides of the common electrode.

13. The amplifier of claim 12 , wherein the first electrodes of the first and second output capacitors and the common electrode are all disposed in a same surface of a semiconductor substrate.

14. The amplifier of claim 10 , wherein the first output inductor comprises a microstrip line.

15. The amplifier of claim 1 , wherein the second, third, fourth and fifth output inductors all comprise a common microstrip line extending from the output terminal of the first gain element, past the output terminal of the second gain element, to the output terminal of the third gain element.

16. An amplifier configured to operate at an operating frequency, the amplifier comprising:

an input port and an output port;

first, second, and third gain elements, each having an input terminal and an output terminal;

an input matching network; and

an output matching network,

wherein the input matching network comprises:

a first microstrip line connected to the input port arid being configured to be an input inductor at the operating frequency of the amplifier,

a second microstrip line extending between the input terminals of the first, second and third gain elements, and

a first split shunt capacitor connecting the first microstrip line to the second microstrip line, and

wherein the output matching network comprises:

a third microstrip line connected to the output port and being configured to be an output inductor at the operating frequency of the amplifier,

a fourth microstrip line extending between the output terminals of the first, second and third gain elements, and

a second split shunt capacitor connecting the third microstrip line to the fourth microstrip line.

17. The amplifier of claim 16 , further comprising:

a first tapered connector that connects the first microstrip line to the first split shunt capacitor; and

a second tapered connector that connects the second split shunt capacitor and the third microstrip line.

18. The amplifier of claim 16 , wherein the first and second split shunt capacitors each comprise a common electrode having a through-hole disposed therein connecting the common electrode to a supply voltage, and a pair of electrodes disposed respectively at opposite sides of the common electrode.

19. The amplifier of claim 18 , wherein the second microstrip line is configured to comprise, at the operating frequency:

a second input inductor connected between a first one of the pair of electrodes of the first split shunt capacitor and the input terminal of the first gain element,

a third input inductor connected between the first one of the pair of electrodes of the first split shunt capacitor and the input terminal of the second gain element,

a fourth input inductor connected between the input terminal of the second gain element and a second one of the pair of electrodes of the second split shunt capacitor, and

a fifth input inductor connected between the first electrode of the second one of the pair of electrodes of the second split shunt capacitor and the input terminal of the third gain element.

20. The amplifier of claim 19 , wherein the second, third, fourth, and fifth input inductors all have substantially a same inductance value.

Assignments (8)
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF MERGER TO 09/05/2018 PREVIOUSLY RECORDED AT REEL: 047230 FRAME: 0133. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047630/0456 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047230/0133 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032851-0001) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 037689/0001 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032851/0001 →
MERGER Recorded May 7, 2013
From: AVAGO TECHNOLOGIES WIRELESS IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 030369/0471 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 19, 2011
From: FUJII, KOHEI
To: AVAGO TECHNOLOGIES WIRELESS IP (SINGAPORE) PTE. LTD.
Reel/Frame 026148/0036 →