IP Library Granted Patent US 8,569,124
Granted Patent B2
US 8,569,124 · App. 13/089,981 · Granted Oct 29, 2013

Method of manufacturing compound semiconductor device with gate electrode forming before source electrode and drain electrode

Inventors: Shinichi Akiyama (Yokohama, JP); Kenji Nukui (Yokohama, JP); Mutsumi Katou (Yokohama, JP); Yoshitaka Watanabe (Yokohama, JP); Tetsuya Itou (Yokohama, JP); Yoichi Fujisawa (Yokohama, JP); Toshiya Sato (Yokohama, JP); Tsutomu Hosoda (Yokohama, JP); Yuuichi Satou (Yokohama, JP)
Assignee: Fujitsu Semiconductor Limited
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Quick Facts
Patent No.
US 8,569,124
App. No.
13/089,981
Granted
Oct 29, 2013
Kind
B2
Abstract

A compound semiconductor device includes a substrate; a compound semiconductor layer formed on the substrate; a first insulating film formed on the compound semiconductor layer; a second insulating film formed on the first insulating film; and a gate electrode, a source electrode, and a drain electrode, each being formed on the compound semiconductor layer, wherein the gate electrode is formed of a first opening filled with a first conductive material via at least a gate insulator, and the first opening is formed in the first insulating film and configured to partially expose the compound semiconductor layer, and wherein the source electrode and the drain electrode are formed of a pair of second openings filled with at least a second conductive material, and the second openings are formed in at least the second insulating film and the first insulating film and configured to partially expose the compound semiconductor layer.

Claims (44)

1. A method of manufacturing a compound semiconductor device, comprising:

forming a compound semiconductor layer on a substrate;

forming a first insulating film on the compound semiconductor layer;

forming a first opening in the first insulating film, the first opening being configured to partially expose the compound semiconductor layer;

forming a first conductive material on the first insulating film via at least a gate insulator in such a manner that the first opening is filled with the first conductive material;

forming a first mask on a portion of the first conductive material corresponding to the first opening;

processing at least the first conductive material with the first mask to form a gate electrode;

forming a second insulating film on the first insulating film so as to cover the gate electrode;

forming a pair of second openings in at least the second insulating film and the first insulating film, the pair of second openings being configured to partially expose the compound semiconductor layer;

forming at least a second conductive material on the second insulating film in such a manner that the second openings are filled with the second conductive material;

forming second masks on portions of the second conductive material corresponding to the second openings;

processing at least the second conductive material using the second masks to form a source electrode and a drain electrode; and

forming a first conductive film on the first insulating film so as to cover the inner surface of the first opening, the first conductive film containing at least TaN,

wherein the first conductive material is formed on the first conductive film, and after the formation of the first conductive material, the substrate is subjected to heat treatment.

2. The method according to claim 1 , wherein

the composition ratio of N of TaN contained in the first conductive film is larger than the composition ratio of Ta of TaN contained in the first conductive film.

3. A method of manufacturing a compound semiconductor device, comprising:

forming a compound semiconductor layer on a substrate;

forming a first insulating film on the compound semiconductor layer;

forming a first opening in the first insulating film, the first opening being configured to partially expose the compound semiconductor layer;

forming a first conductive material on the first insulating film via at least a gate insulator in such a manner that the first opening is filled with the first conductive material;

forming a first mask on a portion of the first conductive material corresponding to the first opening;

processing at least the first conductive material with the first mask to form a gate electrode;

forming a second insulating film on the first insulating film so as to cover the gate electrode;

forming a pair of second openings in at least the second insulating film and the first insulating film, the pair of second openings being configured to partially expose the compound semiconductor layer;

forming at least a second conductive material on the second insulating film in such a manner that the second openings are filled with the second conductive material;

forming second masks on portions of the second conductive material corresponding to the second openings;

processing at least the second conductive material using the second masks to form a source electrode and a drain electrode; and

forming a second conductive film having a work function of 4.5 eV or more;

wherein the gate insulator and the second conductive film are formed so as to cover the inner surface of the first opening, and the first conductive material is formed on the first insulating film with at least the gate insulator and the second conductive film.

4. A method of manufacturing a compound semiconductor device, comprising:

forming a compound semiconductor layer on a substrate;

forming a first insulating film on the compound semiconductor layer;

forming a first opening in the first insulating film, the first opening being configured to partially expose the compound semiconductor layer;

forming a first conductive material on the first insulating film via at least a gate insulator in such a manner that the first opening is filled with the first conductive material;

forming a first mask on a portion of the first conductive material corresponding to the first opening;

processing at least the first conductive material with the first mask to form a gate electrode;

forming a second insulating film on the first insulating film so as to cover the gate electrode;

forming a pair of second openings in at least the second insulating film and the first insulating film, the pair of second openings being configured to partially expose the compound semiconductor layer;

forming at least a second conductive material on the second insulating film in such a manner that the second openings are filled with the second conductive material;

forming second masks on portions of the second conductive material corresponding to the second openings;

processing at least the second conductive material using the second masks to form a source electrode and a drain electrode; and

forming a third conductive film so as to cover inner surfaces of the second openings, the third conductive film having a work function of less than 4.5 eV;

wherein the second conductive material is formed on the second insulating film via the third conductive film provided between the second conductive material and the second insulating film in such a manner that the second openings are filled with the second conductive material.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 9, 2014
From: FUJITSU SEMICONDUCTOR LIMITED
To: TRANSPHORM JAPAN, INC.
Reel/Frame 032865/0131 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 25, 2011
From: AKIYAMA, SHINICHI; NUKUI, KENJI; KATOU, MUTSUMI; WATANABE, YOSHITAKA; ITOU, TETSUYA; FUJISAWA, YOICHI; SATO, TOSHIYA; HOSODA, TSUTOMU; SATOU, YUUICHI
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 026640/0771 →
Priority Claims (1)
JP 2010-107654 · May 7, 2010 · national
Continuity (1)
Related Publication 20110272742A1 · Nov 10, 2011