Multi-level options for power MOSFETS
This document discusses, among other things, a semiconductor device including first and second conductive layers, the first conductive layer including a gate runner and a drain contact and the second conductive layer including a drain conductor, at least a portion of the drain conductor overlying at least a portion of the gate runner. A first surface of the semiconductor device can include a gate pad coupled to the gate runner and a drain pad coupled to the drain contact and the drain conductor.
1. A semiconductor device comprising:
a substrate;
a first device surface overlying the substrate, the first device surface including at least three pads, wherein the at least three pads include:
a drain pad;
a gate pad; and
a source pad;
a plurality of trenched gate structures coupled to the gate pad, the plurality of trenched gate structures configured to control a flow of electrical current between the source pad and the drain pad when a voltage is applied to the gate pad;
a first conductive layer including:
a drain contact, the drain contact coupled to the drain pad;
a gate runner, the gate runner coupled to the gate pad; and
a source contact coupled between the source pad and the plurality of trenched gate structures; and
a second conductive layer, at least a portion of the second conductive layer separated from at least a portion of the first conductive layer using a dielectric, wherein the second conductive layer includes a drain conductor, at least a portion of the drain conductor overlying at least a portion of the gate runner, wherein the drain conductor is coupled to the drain contact.
2. The semiconductor device of claim 1 , wherein a portion of the drain conductor overlies at least a portion of the source contact.
3. The semiconductor device of claim 1 , wherein the drain conductor includes the drain pad.
4. The semiconductor device of claim 3 , including a drain via coupling the drain contact to the drain pad.
5. The semiconductor device of claim 1 , including a gate via configured to couple the gate runner with the gate pad.
6. The semiconductor device of claim 1 , wherein the gate runner includes polycrystalline silicon.
7. The semiconductor device of claim 6 , wherein the gate runner includes a first metal overlying the polycrystalline silicon, wherein the first conductive layer includes the first metal.
8. The semiconductor device of claim 6 , wherein the polycrystalline silicon includes silicided polycrystalline silicon.
9. The semiconductor device of claim 1 , wherein the substrate includes a trench configured to support the gate runner.
10. The semiconductor device of claim 9 , wherein the substrate includes an epitaxial layer and wherein the epitaxial layer includes the trench.
11. The semiconductor device of claim 1 , wherein the second conductive layer includes a gate conductor coupled to the gate runner.
12. The semiconductor device of claim 11 , wherein the gate conductor includes the gate pad.
13. The semiconductor device of claim 11 , wherein at least a portion of the gate conductor overlies at least a portion of the source contact.
14. The semiconductor device of claim 1 , wherein the second conductive layer includes a source conductor coupled to the source contact.
15. The semiconductor device of claim 14 , wherein the source conductor includes the source pad.
16. The semiconductor device of claim 1 , including a third conductive layer, at least a portion of the third conductive layer separating and overlying at least a portion of the second conductive layer using a dielectric.
17. The semiconductor device of claim 16 , wherein the third conductive layer includes the at least three pads.
18. The semiconductor device of claim 1 , wherein the at least three pads each include a top surface substantially co-planar with one another.
19. The semiconductor device of claim 1 , wherein the at least three pads include solderable material.
20. The semiconductor device of claim 1 , wherein the drain contact has a substantially uniform width and extends about a perimeter of the semiconductor device.
21. The semiconductor device of claim 1 , wherein the drain contact has a tapered width and extends parallel to the plurality of trench gate structures.
22. The semiconductor device of claim 1 , wherein the drain contact has a substantially uniform width and extends parallel to the plurality of trench gate structures.
23. The semiconductor device of claim 1 , wherein the drain contact has a tapered width and extends perpendicular to the plurality of trench gate structures.
24. The semiconductor device of claim 1 , wherein the drain contact has a substantially uniform width and extends perpendicular to the plurality of trench gate structures.
25. The semiconductor device of claim 1 , wherein the gate runner includes a metallic compound.