System and method for processing signals in high speed DRAM
A method is disclosed for operating a memory device, including providing a timing signal comprising a plurality of clock cycles, providing an activate signal, and providing a bank address signal. An activate command executes on every first duration of clock cycles, and the bank address signal is high for at least a portion of the first duration of clock cycles. In one embodiment, the first duration of the activate signal is at least four clock cycles, and the bank address signal is at least one clock cycle. A memory device having a row decoder and an active driver is also provided.
1. A memory device, comprising:
bank control logic configured to generate a modified bank address signal by latching a bank address signal to an activate command signal;
an active driver configured to provide a bank activate signal, wherein the active driver is further configured to receive the activate command signal and execute an activate command of the activate command signal at each one of a group of clock cycles, wherein each one of the group of clock cycles is greater than one clock cycle; and
the active driver further configured to receive the modified bank address signal, wherein the modified bank address signal is high for at least a portion of each one of the group of clock cycles, and wherein the at least a portion of each one of the group of clock cycles is greater than one clock cycle.
2. The memory device of claim 1 , wherein the active driver comprises an inverter.
3. The memory device of claim 1 , wherein the active driver comprises a NOR gate and an AND gate.
4. The memory device of claim 3 , wherein the AND gate is configured to receive the activate command signal and the modified bank address signal.
5. The memory device of claim 4 , wherein the NOR gate is configured to receive an output of the AND gate.
6. The memory device of claim 5 , wherein the NOR gate is configured to receive a refresh signal.
7. The memory device of claim 6 , wherein the active driver comprises an inverter configured to receive an output of the NOR gate.
8. The memory device of claim 1 , wherein the bank control logic is further configured to transmit the modified bank address signal to the active driver.
9. The memory device of claim 8 , comprising a command decoder configured to transmit the activate command signal to the active driver.
10. The memory device of claim 9 , comprising control logic, wherein the control logic comprises the command decoder and the active driver.
11. The memory device of claim 1 , comprising a row decoder configured to receive the bank activate signal from the active driver.
12. The memory device of claim 1 , wherein the memory device is a DDR3 SDRAM memory device.
13. The memory device of claim 1 , wherein the memory device is a DDR2 SDRAM memory device.
14. The memory device of claim 1 , wherein each one of the group of clock cycles comprises four clock cycles.
15. A memory device, comprising:
bank control logic configured to transmit a modified bank address signal that transitions to a high state at a first time and transitions to a low state at a second time;
wherein the bank control logic is further configured to generate the modified bank address signal by latching a bank address signal to an activate command signal;
a command decoder configured to transmit the activate command signal that transitions to a high state at a third time and transitions to a low state at a fourth time; and
an active driver configured to receive the modified bank address signal and the activate command signal and configured to transmit a bank activate signal;
wherein the third time is after the first time, and wherein the second time is after the fourth time.
16. The memory device of claim 15 , comprising a row decoder configured to receive the bank activate signal.
17. The memory device of claim 15 , wherein the command decoder is configured to transmit an activate command of the activate command signal after every set of clock cycles, wherein the set of clock cycles is more than one clock cycle.
18. The memory device of claim 17 , wherein a difference between the second time and the first time is greater than on clock cycle.
19. The memory device of claim 17 , wherein the first time occurs while a clock signal is high during a first clock cycle, and wherein the second time occurs while the clock signal is low during a second clock cycle, wherein the second clock cycle is immediately subsequent to the first clock cycle.
20. A memory device configured to receive a timing signal comprising a plurality of clock cycles, the memory device comprising:
a command decoder configured to provide an activate command signal, wherein an activate command executes on every first duration of clock cycles;
bank control logic configured to provide a modified bank address signal, wherein the modified bank address signal for the activate command is high for at least one or more clock cycles and for a time between successive activate commands, wherein the first duration is at least one clock cycle; wherein the bank control logic is further configured to generate the modified bank address signal by latching a bank address signal to an activate command signal; and
an active driver configured to receive the modified bank address signal and the activate command signal and configured to transmit a bank activate signal.
21. The memory device of claim 20 , wherein the active driver is configured to receive a refresh signal.
22. The memory device of claim 20 , comprising a row decoder configured to receive the bank activate signal from the active driver.
23. The memory device of claim 20 , wherein the first duration is more than one clock cycle.
24. The memory device of claim 23 , wherein the first duration is four clock cycles.