Matching signal dynamic range for turbo equalization system

1. A method for reducing a number of bits for representing a value, comprising:

transforming by a processor a first value represented with a first number of bits to a second value represented with a second number of bits, wherein the first number of bits is greater than the second number of bits, comprising:

selecting a target window with a width of a third number of bits, wherein the third number of bits is smaller than the first number of bits, and wherein the target window comprises a window of consecutive bits, the consecutive bits not including the least significant bit of any binary number the target window is applied to; and

scaling by the processor the transformed second value by a scale factor to a third value.

2. The method of claim 1 , wherein transforming comprises:

saturating the first value to a most significant bit (MSB) within the selected target window; and

extracting bits within the selected target window from the saturated value.

3. The method of claim 2 , wherein saturating the first value comprises setting the first value to a value of 2 i −1 if the first value equals or exceeds 2 i , wherein i is the MSB within the selected target window.

4. The method of claim 2 , wherein extracting bits within the selected target window comprises truncating bits outside the selected target window.

5. The method of claim 1 , wherein transforming comprises:

extracting bits within the selected target window from the first value; and

saturating the extracted value to a most significant bit (MSB) within the selected target window.

6. The method of claim 1 , wherein scaling the transformed second value comprises multiplying the transformed second value with a fourth value to a fifth value.

7. The method of claim 6 , wherein scaling further comprises right shifting the fifth value.

8. The method of claim 1 , wherein each of the first value and the third value is a Log-likelihood ratio (LLR).

9. The method of claim 8 , wherein the first value is an LLR value maintained by a signal detector, and wherein the third value is an LLR value fed as an input to an error correction code (ECC) decoder.

10. The method of claim 9 , wherein the ECC decoder is an LDPC decoder.

11. A system for reducing a number of bits for representing a value, comprising:

a receiver configured to:

transform by a processor a first value represented with a first number of bits to a second value represented with a second number of bits, wherein the first number of bits is greater than the second number of bits, wherein transforming comprises:

selecting a target window with a width of a third number of bits, wherein the third number of bits is smaller than the first number of bits, and wherein the target window comprises a window of consecutive bits, the consecutive bits not including the least significant bit of any binary number the target window is applied to; and

scale the transformed second value by a scale factor to a third value; and

an interface coupled to the receiver and configured to receive samples.

12. The system of claim 11 , wherein transforming comprises:

saturating the first value to a most significant bit (MSB) within the selected target window; and

extracting bits within the selected target window from the saturated value.

13. The system of claim 12 , wherein saturating the first value comprises setting the first value to a value of 2 i −1 if the first value equals or exceeds 2 i , wherein i is the MSB within the selected target window.

14. The system of claim 12 , wherein extracting bits within the selected target window comprises truncating bits outside the selected target window.

15. The system of claim 11 , wherein scaling the transformed second value comprises multiplying the transformed second value with a fourth value to a fifth value.

16. The system of claim 15 , wherein scaling further comprises right shifting the fifth value.

17. The system of claim 11 , wherein each of the first value and the third value is a Log-likelihood ratio (LLR).

18. The system of claim 17 , wherein the first value is an LLR value maintained by a signal detector, and wherein the third value is an LLR value fed as an input to an error correction code (ECC) decoder.

19. The system of claim 18 , wherein the ECC decoder is an LDPC decoder.

20. A computer program product for reducing a number of bits for representing a value, the computer program product being embodied in a non-transitory computer readable storage medium and comprising computer instructions for:

transforming a first value represented with a first number of bits to a second value represented with a second number of bits, wherein the first number of bits is greater than the second number of bits, comprising:

selecting a target window with a width of a third number of bits, wherein the third number of bits is smaller than the first number of bits, and wherein the target window comprises a window of consecutive bits, the consecutive bits not including the least significant bit of any binary number the target window is applied to; and

scaling the transformed second value by a scale factor to a third value.

21. The computer program product of claim 20 , wherein transforming comprises:

saturating the first value to a most significant bit (MSB) within the selected target window; and

extracting bits within the selected target window from the saturated value.