Semiconductor device and method for fabricating the same
A semiconductor device includes a plurality of first conductive patterns separated by a damascene pattern, a second conductive pattern buried in the damascene pattern, and a spacer including an air gap between the second conductive pattern and the first conductive patterns.
1. A method for forming a semiconductor device, comprising:
forming a first conductive layer;
forming a damascene pattern and first conductive patterns by etching the first conductive layer;
forming a spacer on sidewalls of the damascene pattern;
forming a second conductive pattern buried in the damascene pattern; and
forming an air gap between the first conductive patterns and the second conductive pattern by etching a portion of the spacer.
2. The method of claim 1 , further comprising:
forming a capping layer for hermetically sealing an upper portion of the air gap.
3. The method of claim 1 , wherein the forming of the damascene pattern comprises:
forming a damascene mask; and
etching the first conductive layer using the damascene mask as an etch barrier.
4. The method of claim 1 , wherein the forming of the spacer comprises:
forming multiple spacers comprising a sacrificial spacer selected from the group consisting of a titanium nitride layer, an aluminum oxide layer, and a silicon layer.
5. The method of claim 4 , wherein the air gap is formed by removing the sacrificial spacer.
6. The method of claim 1 , wherein the forming of the second conductive pattern comprises:
forming a conductive layer filling the damascene pattern with the spacer formed therein; and
forming the second conductive pattern by recessing the conductive layer.
7. The method of claim 6 , further comprising forming a hard mask layer over the second conductive pattern.
8. The method of claim 7 , wherein the forming of the air gap comprises:
planarizing the hard mask layer to expose an upper portion of a sacrificial spacer included within the spacer; and
removing the sacrificial spacer through a wet etch process or a dry etch process.
9. The method of claim 1 , wherein the first conductive patterns comprise storage node contact plugs, and the second conductive pattern comprises a bit line.
10. The method of claim 9 , wherein the storage node contact plugs comprise a polysilicon layer or a tungsten layer.
11. A method for forming a semiconductor device, comprising:
forming a first conductive layer;
forming a damascene pattern and first conductive patterns by etching the first conductive layer;
forming a dual spacer, comprising a sacrificial spacer and a spacer, on sidewalls of the damascene pattern;
forming a second conductive pattern buried in the damascene pattern; and
forming an air gap by etching the sacrificial spacer.
12. The method of claim 11 , wherein the forming of the dual spacer comprises:
forming the sacrificial spacer on the sidewalls of the damascene pattern; and
forming the spacer on sidewalls of the sacrificial spacer.
13. The method of claim 11 , wherein the sacrificial spacer is a titanium nitride layer, and the spacer is a silicon nitride layer.
14. The method of claim 11 , wherein the sacrificial spacer is an aluminum oxide layer or a silicon layer, and the spacer is a silicon nitride layer.
15. The method of claim 11 , wherein the first conductive patterns comprise storage node contact plugs, and the second conductive pattern comprises a bit line.
16. The method of claim 15 , wherein the storage node contact plugs comprise a polysilicon layer.
17. The method of claim 11 , wherein in the forming of the dual spacer,
the sacrificial spacer is formed by oxidizing a sidewall of the first conductive patterns exposed by the damascene pattern.
18. The method of claim 17 , wherein the first conductive patterns comprise a tungsten layer, and the sacrificial spacer comprises a tungsten oxide layer.
19. The method of claim 11 , further comprising:
forming a capping layer for hermetically sealing an upper portion of the air gap.
20. The method of claim 11 , wherein the forming of the second conductive pattern further comprises:
forming a conductive layer filling the damascene pattern with the dual spacer formed therein; and
forming the second conductive pattern by recessing the conductive layer.
21. The method of claim 20 , further comprising forming a hard mask layer over the second conductive pattern.
22. A method for forming a semiconductor device, comprising:
forming a first conductive layer;
forming a damascene pattern and first conductive patterns by etching the first conductive layer;
forming a triple spacer, comprising a first spacer, a sacrificial spacer, and a second spacer, on sidewalls of the damascene pattern;
forming a second conductive pattern buried in the damascene pattern; and
forming an air gap by etching the sacrificial spacer.
23. The method of claim 22 , further comprising:
forming a capping layer for hermetically sealing an upper portion of the air gap.
24. The method of claim 22 , wherein the forming of the second conductive pattern further comprises:
forming a conductive layer filling the damascene pattern with the triple spacer formed therein; and
forming the second conductive pattern by recessing the conductive layer.
25. The method of claim 24 , further comprising forming a hard mask layer over the second conductive pattern.
26. The method of claim 22 , wherein the sacrificial spacer comprises any one selected from the group consisting of a titanium nitride layer, an aluminum oxide layer, and a silicon layer.
27. The method of claim 22 , wherein the first spacer comprises a silicon oxide layer, and the sacrificial spacer comprises a titanium nitride layer, and the second spacer comprises a silicon nitride layer.
28. The method of claim 22 , further comprising:
removing the first spacer after the etching of the sacrificial spacer.
29. The method of claim 22 , wherein the first spacer comprises a tungsten oxide layer, and the sacrificial spacer comprises a titanium nitride layer, and the second spacer comprises a silicon nitride layer.
30. The method of claim 22 , wherein the forming of the triple spacer comprises:
stacking a first spacer layer and a second spacer layer over a substrate structure including the damascene pattern;
forming the sacrificial spacer and the first spacer by selectively etching the second spacer layer and the first spacer layer;
forming a third spacer layer over a substrate structure comprising the sacrificial spacer; and
forming the second spacer by selectively etching the third spacer layer.
31. The method of claim 22 , wherein in the forming of the triple spacer,
the first spacer is formed by oxidizing a sidewall of the first conductive patterns exposed by the damascene pattern.
32. The method of claim 31 , wherein the first conductive patterns comprise a tungsten layer, and the first spacer comprises a tungsten oxide layer.
33. The method of claim 22 , wherein the first conductive patterns comprise storage node contact plugs, and the second conductive pattern comprises a bit line.
34. The method of claim 33 , wherein the storage node contact plugs comprise a polysilicon layer or a tungsten layer.