Method and apparatus for implementing cache coherency of a processor
View Patent ↗An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.
1. A processor, comprising:
a plurality of processor cores;
a data switch interconnect, coupled with a data cache of each of the plurality of processor cores, to move information among the plurality of processor cores, without being directly coupled to an instruction cache of at least one of the plurality of processor cores;
a messaging network configured to move information between the plurality of processor cores and a plurality of communication ports, the messaging network being directly coupled with the instruction cache of the at least one of the plurality of processor cores without being directly coupled to the data cache of each of the plurality of processor cores; and
a level 2 cache coupled to the data switch interconnect to share dirty cache lines across the plurality of processor cores, wherein cache coherence for the level 2 cache is maintained using a Modified, Own, Shared, Invalid (MOSI) protocol.
2. The processor of claim 1 , wherein the data switch interconnect comprises a ring arrangement with a plurality of ring elements coupled to the respective data caches of the plurality of processor cores and a respective portion of the level 2 cache without being directly coupled to an instruction cache of at least one of the plurality of processor cores.
3. The processor of claim 2 , wherein the level 2 cache coupled to the data switch interconnect is configured to store information accessible to the plurality of processor cores.
4. The processor of claim 2 , wherein the data switch interconnect is configured to provide one or more datapaths to main memory via a first memory bridge and a second memory bridge.
5. The processor of claim 2 , further comprising:
a memory bridge coupled to the data switch interconnect and at least one communication port and configured to communicate with the data switch interconnect and the communication port.
6. The processor of claim 1 , further comprising:
a messaging ring component or messaging ring station coupled to the plurality of processor cores.
7. The processor of claim 6 , in which the messaging ring component or messaging ring station is directly coupled to the instruction cache of the at least one of the plurality of processor cores.
8. The processor of claim 6 , in which the messaging ring component or messaging ring station is situated in a data path between a first processor core of the plurality of processor cores and a second processor core of the plurality of processor cores.
9. The processor of claim 8 , in which the messaging ring component or messaging ring station is configured such that the data path provides communication between the first processor core and the second processor core without going through a memory element.
10. The processor of claim 9 , in which the first processor core or the second processor core is to communicate with the memory element by using one or more memory bridges via the messaging ring component or messaging ring station or the data switch interconnect.
11. The processor of claim 6 , in which an OWN state for the MOSI protocol is employed to maintain the cache coherency when sharing the dirty cache lines.
12. The processor of claim 1 , wherein each of the plurality of processor cores is capable of running a different operating system than the other processor cores.
13. The processor of claim 1 , further comprising a status processor core configured to ensure that each of the plurality of processor cores is functioning properly.
14. The processor of claim 1 ,
wherein each of the processor cores includes an instruction scheduler configured to sequentially schedule at least one instruction from each of a plurality of threads that have an instruction to schedule, skipping stalled threads from among the plurality of threads that lack an instruction to schedule.
15. The processor of claim 14 , wherein the stalled threads are empty threads that do not include any instructions.
16. The processor of claim 14 , wherein the instruction scheduler is configured to perform the scheduling of the plurality of threads that have an instruction to schedule by:
pre-allocating, for each of the plurality of threads, a corresponding instruction allocation having a predetermined number of cycles;
determining, after the pre-allocating, that a first thread from among the plurality of threads has instruction data less than the corresponding instruction allocation resulting in an unused portion of the corresponding instruction allocation; and
scheduling an instruction allocation associated with a second thread to begin during the unused portion of the first thread instruction allocation.
17. The processor of claim 16 , wherein the predetermined number of cycles is different for each of the plurality of threads.
18. The processor of claim 16 , wherein the predetermined number of cycles for each corresponding instruction allocation are the same for each of the plurality of threads.
19. The processor of claim 16 , wherein each of the stalled threads are in a sleep state.
20. The processor of claim 19 , further comprising hazard detection logic configured to place the stalled threads in the sleep state based on latency information.