Memory array having a programmable word length, and method of operating same
View Patent ↗A memory cell array and device having a memory cell array (i.e., an integrated circuit device, for example, a logic device (such as, a microcontroller or microprocessor) or a memory device (such as, a discrete memory)) including electrically floating body transistors in which electrical charge is stored in the body of the transistor, and techniques for reading, controlling and/or operating such memory cell array and such device. The memory cell array and device include a variable and/or programmable word length. The word length relates to the selected memory cells of a selected row of memory cells (which is determined via address data). In one embodiment, the word length may be any number of memory cells of a selected row which is less than or equal to the total number of memory cells of the selected row of the memory array. In one aspect, write and/or read operations may be performed with respect to selected memory cells of a selected row of the memory array, while unselected memory cells of the selected row are undisturbed.
1. A method for biasing an integrated circuit device comprising:
applying a plurality of voltage potentials using at least one of write circuitry and read circuitry to at least one first memory cell including a first transistor of a plurality of memory cells arranged in a matrix of rows and columns, wherein applying a plurality of voltage potentials to the at least one first memory cell comprises:
applying a first voltage potential to a source region of the first transistor via a source line;
applying a second voltage potential to a drain region of the first transistor via a bit line;
applying a third voltage potential to a body region of the first transistor via a word line coupled to a gate disposed over the body region, wherein the body region is electrically floating and programmable to store one of a plurality of data states which are representative of an amount of charge stored in the body region.
2. The method of claim 1 , further comprising applying a plurality of de-select voltage potentials using at least one of the write circuitry and the read circuitry to at least one second memory cell including a second transistor of the plurality of memory cells.
3. The method of claim 2 , wherein applying a plurality of de-select voltage potentials comprises increasing a voltage potential applied to a drain region of the second transistor from the voltage potential applied to the drain region of the second transistor during a hold operation to inhibit at least one of a write operation and a read operation.
4. The method of claim 2 , wherein applying a plurality of de-select voltage potential comprises applying a constant voltage potential to the drain region of the second transistor, wherein the constant voltage potential is higher than a voltage potential applied to the drain region of the second transistor during a hold operation.
5. The method of claim 1 , further comprising increasing the first voltage potential applied to the source line from the first voltage potential applied to the source line during a hold operation to perform at least one of a write logic low operation, a write logic high operation, and a read operation.
6. The method of claim 5 , further comprising increasing the third voltage potential applied to the word line from the third voltage potential applied to the word line during the hold operation to perform at least one of the write logic low operation, the write logic high operation, and the read operation.
7. The method of claim 6 , further comprising increasing the second voltage potential applied to the bit line from the second voltage potential applied to the bit line during the hold operation to perform the write logic low operation.
8. The method of claim 7 , wherein the second voltage potential applied to the bit line is increased before increasing the first voltage potential applied to the source line.
9. The method of claim 8 , wherein the second voltage potential applied to the bit line is equal to the third voltage potential applied to the word line during the write logic low operation.
10. The method of claim 6 , further comprising maintaining the second voltage potential applied to the bit line at the second voltage potential applied to the bit line during the hold operation to perform the write logic high operation.
11. The method of claim 10 , wherein the third voltage potential applied to the word line is higher than the second voltage potential applied to the bit line during the write logic high operation.
12. The method of claim 6 , further comprising maintaining the second voltage potential applied to the bit line at the second voltage potential applied to the bit line during the hold operation to perform the read operation.
13. The method of claim 12 , wherein the third voltage potential applied to the word line is lower than the second voltage potential applied to the bit line during the read operation.
14. The method of claim 1 , further comprising decreasing the first voltage potential applied to the source line from the first voltage potential applied to the source line during a hold operation to perform at least one of a write logic low operation, a write logic high operation, and a read operation.
15. The method of claim 14 , further comprising increasing the third voltage potential applied to the word line from the third voltage potential applied to the word line during the hold operation to perform at least one of the write logic low operation, the write logic high operation, and the read operation.
16. The method of claim 15 , further comprising decreasing the second voltage potential applied to the bit line from the second voltage potential applied to the bit line during the hold operation to perform the write logic low operation.
17. The method of claim 16 , wherein the second voltage potential is equal to the third voltage potential during the write logic low operation.
18. The method of claim 15 , further comprising maintaining the second voltage potential applied to the bit line at the second voltage potential applied to the bit line during the hold operation to perform at least one of the write logic low operation and the read operation.
19. The method of claim 18 , wherein the third voltage potential applied to the word line is lower than the second voltage potential applied to the bit line during the write logic high operation.
20. The method of claim 18 , wherein the third voltage potential applied to the word line is higher than the second voltage potential applied to the bit line during the read operation.