Multilayer wiring substrate
To provide a multilayer wiring substrate which can prevent migration of copper between wiring traces to thereby realize a higher degree of integration, a solder resist layer 25 having a plurality of openings 35, 36 is disposed on a top surface 31 side, and IC-chip connection terminals 41 and capacitor connection terminals 42 are buried in an outermost resin insulation layer 23 in contact with the solder resist layer 25 . Each of the IC-chip connection terminals 41 and the capacitor connection terminals 42 is composed of a copper layer 44 and a plating layer 46 covering the outer surface of the copper layer 44 . A conductor layer 26 present at the interface between the solder resist layer 25 and the resin insulation layer 23 is composed of a copper layer 27 and a nickel plating layer 28 covering the outer surface of the copper layer 27.
1. A multilayer wiring substrate comprising a laminate structure in which a plurality of resin insulation layers made primarily of a same resin insulation material, and a plurality of wiring conductor portions are laminated alternately in multilayer arrangement, a plurality of first-main-surface-side connection terminals being disposed on a first main surface side of the laminate structure, a plurality of second-main-surface-side connection terminals being disposed on a second main surface side of the laminate structure, the plurality of wiring conductor portions being formed in the plurality of resin insulation layers and interconnected by means of via conductors whose diameters increase toward the first main surface side or the second main surface side, wherein:
a solder resist layer having a plurality of openings is disposed on the first main surface side or the second main surface side of the laminate structure;
each of the plurality of first-main-surface-side connection terminals or the plurality of second-main-surface-side connection terminals comprises a copper layer and a coating metallic layer entirely covering a top end surface of the copper layer, and is at least partially embedded in an outermost resin insulation layer in contact with the solder resist layer;
a top end surface of the coating metallic layer is at least partially covered by and in contact with the solder resist layer, and the top end surface of the coating metallic layer that is covered by and in contact with the solder resist layer does not comprise gold;
each of outermost wiring conductor portions present at an interface between the solder resist layer and the outermost resin insulation layer comprises a copper layer and a conductive metallic layer covering a top end surface of the copper layer; and
the conductive metallic layer comprises at least one conductive metal selected from gold, chromium, tungsten, platinum, palladium, tin, lead, nickel, cobalt, molybdenum, tantalum, and titanium.
2. The multilayer wiring substrate according to claim 1 , wherein the outermost wiring conductor portions are embedded in the outermost resin insulation layer.
3. The multilayer wiring substrate according to claim 1 , wherein the solder resist layer is disposed on the first main surface side of the laminate structure, and a plurality of IC-chip connection terminals, to which an IC chip is to be connected, are present on the first main surface side as the first-main-surface-side connection terminals.
4. The multilayer wiring substrate according to claim 1 , wherein the coating metallic layer of each of the plurality of first-main-surface-side connection terminals or the plurality of second-main-surface-side connection terminals, and the conductive metallic layer of each of the outermost wiring conductor portions are made primarily of nickel or gold.
5. The multilayer wiring substrate according to claim 4 , wherein each of the coating metallic layer and the conductive metallic layer is made primarily of nickel.
6. The multilayer wiring substrate according to claim 1 ,
wherein each coating metallic layer comprises a nickel plating layer and a gold plating layer,
wherein the nickel plating layer covers the top end surface of the copper layer, and
wherein the gold plating layer covers only a portion of the nickel plating layer exposed from an opening of the solder resist layer.
7. The multilayer wiring substrate according to claim 1 , wherein the terminal outer surfaces of the first-main-surface-side connection terminals or the second-main-surface-side connection terminals are recessed from an outer surface of the solder resist layer.
8. The multilayer wiring substrate according to claim 6 , wherein the solder resist layer is in contact with a peripheral portion of the nickel plating layer which covers the copper layer.
9. The multilayer wiring substrate according to claim 1 , wherein the via conductors formed in the plurality of resin insulation layers increase in diameter from the first main surface side toward the second main surface side.
10. The multilayer wiring substrate according to claim 1 , wherein the solder resist layer and the outermost resin insulation layer are primarily comprised of the same resin insulation material.