Recessed gate silicon-on-insulator floating body device with self-aligned lateral isolation
View Patent ↗Embodiments of a manufacturing process for recessed gate devices on silicon-on-insulator (SOI) substrate with self-aligned lateral isolation are described. This allows the creation of true in-pitch recessed gate devices without requiring an extra isolation dimension. A lateral isolation trench is formed between pairs of recessed gate devices by etching the silicon-on-insulator area down to a buried oxide layer on which the silicon-on-insulator layer is formed. The position of the trench is self-aligned and defined by the gate width and the dimension of spacers disposed on either side of the gate. The isolation trench is filled with a dielectric material and then etched back to the middle of the SOI body and the remaining volume is filled with a doped conductive material. The doped conductor is subject to a thermal cycle to create source and drain regions of the device through out-diffusion of the doped material.
1. A method for manufacturing a memory array, the method comprising:
forming a plurality of recessed gate devices on a silicon-on-insulator substrate over a buried oxide layer, the plurality of recessed gate devices defining the memory array;
defining an insulative spacer region on opposing sides of a recessed transistor gate associated with one of the plurality of recessed gate devices;
etching the silicon-on-insulator substrate until the buried oxide layer is reached to form a lateral isolation trench aligned to the recessed transistor gate by a width of the insulative spacer region;
partially filling the lateral isolation trench with a dielectric fill material;
filling a remaining portion of the lateral isolation trench with doped polysilicon; and
thermally cycling the doped polysilicon to create source and drain regions for each recessed gate device.
2. The method of claim 1 wherein recessed transistor gate extends into the silicon-on-insulator substrate further than the source and drain regions.
3. The method of claim 2 wherein each recessed gate device comprises a floating body region and spacers disposed on opposite sides of a gate region.
4. The method of claim 3 wherein the lateral isolation trench defines a self-aligned contact area for each recessed gate device adjacent the lateral isolation trench.
5. The method of claim 4 wherein the spacers comprise a silicon nitride material placed adjacent to the floating body region.
6. The method of claim 3 wherein the source and drain regions extend from the lateral isolation trench to the gate region.
7. The method of claim 3 wherein the source and drain regions extend from the lateral isolation trench and do not contact the gate region to produce an underlapped device array in order to reduce a gate induced drain leakage effect associated with each recessed gate device of the array.
8. The method of claim 4 wherein the lateral isolation trench is configured to a cross section selected from the group consisting of: substantially vertical sides extending from a top surface to the buried oxide layer, tapered sides extending inwardly from a top surface to the buried oxide layer, and tapered sides extending outwardly from a top surface to the buried oxide layer.
9. The method of claim 3 wherein a width of the lateral isolation trench is defined by a width of the spacers disposed on opposite sides of the gate region.
10. At least one non-transitory processor readable storage medium storing a computer program of instructions configured to be readable by at least one processor for instructing the at least one processor to execute a computer process for performing the method as recited in claim 1 .