Field side sub-bitline nor flash array and method of fabricating the same
Field Side Sub-bitline NOR-type (FSNOR) flash array and the methods of fabrication are disclosed. The field side sub-bitlines of the invention formed with the same impurity type as the memory cells' source/drain electrodes along the two sides of field trench oxide link all the source electrodes together and all the drain electrodes together, respectively, for a string of semiconductor Non-Volatile Memory (NVM) cells in a NOR-type flash array of the invention. Each field side sub-bitline is connected to a main metal bitline through a contact at its twisted point in the middle. Because there are no contacts in between the linked NVM cells' electrodes in the NOR-type flash array of the invention, the wordline pitch and the bitline pitch can be applied to the minimum geometrical feature of a specific technology node. The NOR-type flash array of the invention provides at least as high as those in the conventional NAND flash array in cell area density.
1. A nonvolatile memory (NVM) device comprising:
a memory cell array of NVM cells organized in rows and columns on a substrate, each cell having a charge storing material, a control gate, a first source/drain electrode and a second source/drain electrode;
a plurality of row lines, each connecting the control gates of cells in one row and running in a first direction;
a plurality of field isolations arranged in a pattern that shifts a fraction of one column pitch in the first direction along the memory cell array of NVM cells;
a plurality of column lines running in a second direction and being disposed above the row lines; and
a plurality of sub-bitlines running along two sides of field isolation walls, each sub-bitline being made up of a upper segment and a lower segment running along one side of one field isolation, the upper segment connecting the second source/drain electrodes of a first number of consecutive cells in one column, the lower segment connecting the first source/drain electrodes of a second number of consecutive cells in the adjacent column, the upper segment and the lower segment at a first layer being connected to a common column line at a second layer via one of a plurality of electrical contacts;
wherein the first number and the second number of the consecutive cells comprise no electrical contact being connected to the column lines.
2. The nonvolatile memory device according to claim 1 , wherein an impurity of a conductivity type opposite to that of the substrate forms the source/drain electrodes and the sub-bitlines running in the second direction along two sides of the field isolations and crossing a plurality of silicon active regions where the electrical contacts are landed on.
3. The nonvolatile memory device according to claim 2 , further comprising:
a plurality of semiconductor regions implanted by the impurity of the conductivity type extend in the second direction beyond the regions of the field isolations by a manufacturing process.
4. The nonvolatile memory device according to claim 1 , wherein the field isolations are used to separate column-adjacent sub-bitline-pairs, and wherein depths of the filed isolations are deeper than junction depths of the sub-bitlines.
5. The nonvolatile memory device according to claim 1 , wherein a shift of the fraction of one column pitch of the field isolation pattern in the first direction occurs at every crossing of the upper and lower segments.
6. The nonvolatile memory device according to claim 1 , wherein one of two adjacent sub-bitlines laying along two sides of each common field isolation is terminated on a first side and the second sub-bitline on a second side extends across and continuously runs along the first side where a shift of the fraction of one column pitch of the field isolation pattern in the first direction occurs.
7. The nonvolatile memory device according to claim 6 , wherein the second sub-bitline is connected to a corresponding column line by an electrical contact.
8. The nonvolatile memory device according to claim 1 , wherein the NVM cells are substantially 4F 2 cells where F represents the minimum feature size of a process technology node.
9. The nonvolatile memory device according to claim 1 , wherein the sub-bitlines are formed by using the same conductivity type of impurity as the first source/drain electrodes and the second source/drain electrodes.
10. The nonvolatile memory device according to claim 1 , wherein the charge storing material is made of one selected from the group consisting of conducting floating gate, nitride dielectric film and nano-crystal grains.
11. The nonvolatile memory device according to claim 1 , which is a NOR-type flash memory device.