IP Library › Granted Patent US 8,673,721
Granted Patent B2
US 8,673,721 · App. 13/117,489 · Granted Mar 18, 2014

Three-dimensional semiconductor memory device and method for manufacturing the same

Inventors: Nakanishi Toshiro (Seongnam-si, KR); Choong Man Lee (Seongnam-si, KR)
Assignee: Samsung Electronics Co., Ltd.
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Quick Facts
Patent No.
US 8,673,721
App. No.
13/117,489
Granted
Mar 18, 2014
Kind
B2
Abstract

A three-dimensional semiconductor memory device includes a stacked structure including a plurality of conductive patterns, an active pillar penetrating the stacked structure, and a data storage pattern between the active pillar and the conductive patterns, wherein the active pillar includes a vertical semiconductor pattern penetrating the stacked structure and protruding semiconductor patterns between the vertical semiconductor pattern and the data storage pattern, the protruding semiconductor patterns having a different crystalline structure from that of the vertical semiconductor pattern.

Claims (17)

1. A three-dimensional semiconductor memory device, comprising:

a stacked structure including a plurality of conductive patterns;

an active pillar penetrating the stacked structure; and

a data storage pattern between the active pillar and the conductive patterns,

wherein the active pillar includes a vertical semiconductor pattern penetrating the stacked structure and protruding semiconductor patterns between the vertical semiconductor pattern and the data storage pattern, the protruding semiconductor patterns having a different crystalline structure from that of the vertical semiconductor pattern.

2. The three-dimensional semiconductor memory device as claimed in claim 1 , wherein the active pillar includes a discontinuous boundary surface between the vertical semiconductor pattern and the protruding semiconductor patterns.

3. The three-dimensional semiconductor memory device as claimed in claim 1 , wherein a mean grain size in the protruding semiconductor pattern is larger than the mean grain size in the vertical semiconductor pattern.

4. The three-dimensional semiconductor memory device as claimed in claim 1 , wherein the stacked structure includes insulation patterns between the conductive patterns, the vertical semiconductor pattern including a first thickness adjacent to the insulation patterns and a second thickness, thicker than the first thickness, adjacent to the conductive pattern.

5. The three-dimensional semiconductor memory device as claimed in claim 1 , wherein the protruding semiconductor patterns have ring shapes surrounding the vertical semiconductor pattern.

6. The three-dimensional semiconductor memory device as claimed in claim 1 , wherein the vertical semiconductor pattern has a hollow cylinder shape or a pillar shape.

7. The three-dimensional semiconductor memory device as claimed in claim 1 , wherein the data storage pattern includes a plurality of data storage patterns at least partially separated from each other along a vertical direction.

8. The three-dimensional semiconductor memory device as claimed in claim 7 , wherein the data storage pattern further comprises:

a gate insulation layer contacting the protruding semiconductor pattern;

an inter-gate insulation layer contacting the conductive pattern; and

a floating gate electrode between the gate insulation layer and the inter-gate insulation layer.

9. The three-dimensional semiconductor memory device as claimed in claim 7 , wherein the data storage patterns are completely separated from each other, each data storage pattern extending along an upper surface and a lower surface of the protruding semiconductor pattern.

10. The three-dimensional semiconductor memory device as claimed in claim 7 , wherein the data storage patterns are completely separated from each other, each data storage pattern extending along an upper surface and a lower surface of the conductive pattern.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 27, 2011
From: NAKANISHI, TOSHIRO; LEE, CHOONG MAN
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 026427/0850 →
Priority Claims (1)
KR 10-2010-0050479 · May 28, 2010 · national
Continuity (1)
Related Publication 20110294290A1 · Dec 1, 2011